[AK2331]
Digital AC Timing
Serial interface timing
The AK2331 writes data via the three-wire synchronous serial interface by means of CSN, SCLK,
and SDATA.
SDATA (serial data) consists of a register address (starting from the MSB, A3 to A0) and control
data (starting from the MSB, D7 to D0).
<1> CSN (chip select) is normally set to the high level.
When CSN is set to the low level, the serial interface becomes active.
<2> When a write operation is performed, an address and data are input in synchronization with the
rising edges of 12 SCLK clock pulses while CSN is low.
<3> A write setting is made on the assumption that 12 clock pulses are input from SCLK while CSN is
low.
Note that if clock pulses more than or less than 12 clock pulses are input, data cannot be set
correctly.
tCSLH
tCSHH
tCSS
CSN
tWH
tWL
SCLK
tDS
A3
tDH
A1
A2
A0
D7
D6
D1
D0
SDATA
Rising and falling times
tR
tF
SCLK
VIH
VIL
Parameter
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
Symbol
tCSS
tDS
tDH
tWH
tWL
tCSLH
tCSHH
Condition
Min.
100
100
100
500
500
100
100
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
CSN low hold time
CSN high hold time
VOUT[7:0]=
0x10↔0xEF
Until output reaches
the half LSB of the final
value.
DAC output setting
time
tLDD
300
μs
RS=2.2kΩ,
L=22kΩ,
CL=1000pF
SCLK rising time
SCLK falling time
tR
tF
100
100
ns
ns
Note Digital input timing measurements are made at 0.5DVDD for rising and falling edges.
MS0903-E-00
2008/03
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
