[AK2331]
D0
2.2) VREF registers
Address
Data
A3
1
A2
0
A1
0
A0
0
D7
D6
D5
D4
D3
D2
D1
DA3REF1
DA3REF0
DA2REF1
DA2REF0
DA1REF1
DA1REF0
DA0REF1
DA0REF0
0
0
0
0
0
0
0
0
Initial value
DA3REF1
DA3REF0
to
to
Remarks
DAC reference voltage
DA0REF1
DA0REF0
0
0
1
1
0
1
0
1
VSS (internal)
AVDD (internal)
AVDD/2 (internal)
VREF (external)
2.3) AVDD/2 register
Address
Data
A3
1
A2
0
A1
1
A0
0
D7
D6
D5
D4
D3
D2
D1
D0
－
－
－
－
AVDD2O3
AVDD2O2
AVDD2O1
AVDD2O0
0
0
0
0
0
0
0
0
Initial value
Function
Data
Item
Remarks
0
1
Bypasses the DAC and
outputs the AVDD/2 level
through buffer.
AVDD2O3
to
AVDD2O0
Internal AVDD/2
output
DAC output
Note Internal generated AVDD/2 level can be output to VOUT0 to VOUT3 pins by setting this register.
2.4) BUFON register
Address
A2 A1
Data
A3
1
A0
1
D7
D6
D5
D4
D3
D2
D1
D0
－
－
－
－
BUFON3
BUFON2
BUFON1
BUFON0
0
1
0
0
0
0
0
0
0
0
Initial value
Function
Data
Item
Remarks
0
1
BUFON3
to
BUFON0
DAC buffer
operation
Powers down buffer and
outputs Hi-Z.
Buffer output
2.5) Software reset register
Address
Data
D3
A3
1
A2
1
A1
0
A0
0
D7
0
D6
0
D5
0
D4
D2
0
D1
0
D0
0
SRST[7:0]
Initial value
0
0
When the SRST[7:0] register is set to 0xAA (10101010), a software reset is performed.
This setting initializes all registers.
Upon completion of a software reset, the register is set to 0.
MS0903-E-00
2008/03
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
