AK2306 参数 Datasheet PDF下载

ASAHI KASEI

[AK2306/LV]

FUNCTIONAL DESCRIPTION

PCM Data Interface

AK2306 supports the following 3 PCM data formats

- Long Frame Sync(LF)

- Short Frame Sync(SF)

- GCI

PCM data of both channels are multiplexed and interfaced through the common pins(DR,DX).The first 8bit is defined

as B1 channel and the seconds 8bit is defined as B2 channel in the PCM data stream.

The order of PCM data is MSB first in each channel.

Selection of the interface mode

The GCI and ordinary PCM interface(LF,SF) are selectable through the CPU register as following table.

LF and SF is automatically selected by AK2306 by means of detecting the length of 8KHz frame signal.

Register for PCM Interface mode select (Address:101 Bit:0)

PCMIF

PCM Interface

0

1

LF or SF

GCI

Comments

LF/SF are selected automatically

∗

Default on power-on reset =LF/SF mode(PCMIF=0).

LONG FRAME( LF ) / SHORT FRAME ( SF )

Automatic LF/SF selection

AK2306 monitors the duration of the “H” level of FS and automatically selects LF or SF interface format.

period of FS=”H”

more than 2 clocks of BCK

1 clock of BCK

Timing of the interface

Interface format

LF

SF

8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.

Although there are 64 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data for AK2306 occupy

first and second time slot for channel 0 and channel 1,respectively as is indicated in figures of next page.

- Frame Sync signal (FS)

8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock

of the LSI is generated based on this FS signal.

- Bit Clock (BCLK)

BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 4.096MHz by 64kHz step.

- Position of the Ch0,Ch1 PCM data in the DX/DR data flow

B1 and B2 channel of the PCM data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B

register.

MS0093-E-04

9

2001/11