ASAHI KASEI
[AK2306/LV]
PIN FUNCTION
Pin# Name
1
VFTP1
I/O
I
Function
Positive analog input of the transmit OPamp(AMPT1) for channel 1.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST1.
Negative analog input of the transmit OPamp(AMPT1) for channel 1.
Output of the transmit OPamp(AMPT1) for channel 1.
The external feedback resister is connected between this pin and VFTP1.
Output of the receive OPamp(AMPR1) for channel 1.
Negative analog input of the receive OPamp(AMTR1) for channel 1.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR1.
Analog Output equivalent to the received PCM data for channel 1.
Output gain is adjusted by the GA1R.
Negative analog input of the transmit OPamp(AMPT0) for channel 0.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST0.
Positive analog input of the transmit OPamp(AMPT0) for channel 0.
Output of the transmit OPamp(AMPT0) for channel 0.
The external feedback resister is connected between this pin and VFTP0.
Analog Output equivalent to the received PCM data for channel 0.
Output gain is adjusted by the GA0R
Negative analog input of the receive OPamp(AMTR0) for channel 0.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR0.
Output of the receive OPamp(AMPR0) for channel 0.
Serial output of PCM data.
The channel 1 data is output following the channel 0 data. The PCM data rate is
synchronized with BCLK. This output remains in the high impedance state except for the
period of transmitting PCM data.
Serial input of PCM data.
The channel 1 data is received following the channel 0 data. The PCM data rate is
synchronized with BCLK.
Frame sync input.
This clock is input for the internal PLL which gerenates the internal system clocks. FS
must be 8kHz clock which is synchronized with BCLK.
Bit clock of PCM data interface.
This clock defines the input/output timing of DX and DR.
The frequency of BCLK should be 64 x N kHz(128k – 4096kHz).
2
3
4
5
VFTN1
GST1
GSR1
VFR1
I
O
O
I
6
22
VR1
VFTN0
O
I
23
21
17
19
VFTP0
GST0
VR0
VFR0
I
O
O
I
20
10
GSR0
DX
O
O
11
DR
I
8
FS
I
9
BCLK
I
MS0093-E-04
6
2001/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
