ASAHI KASEI
[AK2306/LV]
GCI ( General Circuit Interface )
GCI format is used for ISDN application. The data format and clocking is showed as Fig X.
timing of the interface
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy
first and second time slot for channel 0 and channel 1,respectively.
Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz GCI. All the internal clock
of the LSI is generated based on this FS signal. High level duration of the FS is 1 clock period of BCLK.
Bit Clock (BCLK)
BCLK defines the GCI data rate. The bit rate of GCI data is half of BCLK. BCLK can be varied from 512kHz to 4.096MHz by
128kHz step.
Position of the Ch0,Ch1 GCI data in the DX/DR data flow
B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register
as same way as PCM interface.
CH0,1selection( Address:100 Bit:5)
SEL2B
CH0
CH1
B2
Remarks
Default
on Reset
0
B1
1
B2
B1
<2ch Multiplex>
FS
BCLK
B1 ch
B2 ch
DX
DR
1
1
2
2
3
3
4
4
5
6
6
7
7
8
8
1
1
2
3
3
4
4
5
6
6
7
7
8
8
Don’t
care
Don’t
care
5
2
5
SEL2B=0 =>
SEL2B=1 =>
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
<Non Multiplex>
Not supported
! Important Notice
Please don’t stop feeding FS and BCLK except Full power down mode.
Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output
is not guaranteed.
MS0093-E-04
11
2001/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
