[AK1542A]
14. Typical Evaluation Board Schematic
RFOUT
AK1542A
18
18
Loop Filter
100pF
R3
100pF
VCO
CP
REFIN
VREF
C1
R2'
R2
18
C3
220nF
SWIN
CPZ
C2
100pF
100pF
RFINP
RFINN
BIAS
27k
51
Fig. 14 Typical Evaluation Board Schematic
Note 1) The [CPZ] pin should be connected to the R2 and C2, which are intermediate nodes, even if the Fast Lock Up is
not used. Therefore, R2 must be connected to the [CP] pin, while C2 must be connected to the ground.
Note 2) In Fast Lock Up mode, R2 and R2’ are connected in parallel by internal switching. For calculation of loop band
width and phase margin at Fast Lock Up mode, the resistance should be considered as parallel of R2 and R2’.
Note 3) It is recommended that the exposed pad at the center of the backside should be connected to the ground.
Note 4) Test pins (TEST1 to 3) should be connected to the ground.
MS1399-E-00
2012/3
- 33 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
