[AK1542A]
2. Power-up Sequence
PVDD,CPVDD
PDN1
50s
1.8V
On-chip LDO
0V
(1.8V)
Refin must be input before setting [PDN2] to “High”
Refin
Don’t care
input
H or L
Registers can be written
Write to register
After more than 50s from the [PDN1] is set to “High”
Here [PDN1] is set to “High” after or at the same time as power-up.
PDN2(PLL)
CP
HiZ
Output(*1)
*1 CP output is not defined before writing the data in
all addresses of the register. After writing them,
CP output can be controlled by register.
Fig. 13 Power Sequence
MS1399-E-00
2012/3
- 32 -