[AK1542A]
4.2 Digital Lock Detect
In the digital lock detect, the [LD] pin outputs is ”Low” every time when the frequency is set. And the [LD] pin outputs “High”
(which means the locked state) when a phase error smaller than T is detected for N times consecutively. If the phase error
larger than T is detected for N times consecutively when the [LD] pin outputs “High”, the [LD] pin outputs “Low”(which means
the unlocked state).
The threshold counts for lock detection N could be set by D[18:17]={LDCNTSEL[1:0]} in <Address4>.
{LDCNTSEL[1:0]} settings and corresponding counts (N) are as follows:
00: N = 7
01: N = 15
10: N = 31
11: N = 63
The lock detect signal is shown below:
Reference clock
PFD clock
VCO divide clock
Phase detector output
Invalid
Invalid
Valid
Invalid
Valid
When “Invalid” is detected consecutively
for N times, LD outputs “High”
LD output
Fig. 8 Digital Lock Detect Operations
MS1399-E-00
2012/3
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AKM [ ASAHI KASEI MICROSYSTEMS ]
