[AK09916]
10.1.3. READ Instruction
When the R/W bit is set to “1”, AK09916 performs read operation.
If a master IC generates an acknowledge instead of a stop condition after AK09916 transfers the data at a
specified address, the data at the next address can be read.
Address can be 00h to 18h, 30h to 32h. When the address is 00h to 18h, the address is incremented 00h
01h 02h 03h 10h 11h ... 18h, and the address goes back to 00h after 18h. When the address
is 30h to 32h, the address goes back to 30h after 32h. AK09916 supports current address read and random
address read.
10.1.3.1. Current Address READ
AK09916 has an address counter inside the LSI chip. In current address read operation, the data at an address
specified by this counter is read.
The internal address counter holds the next address of the most recently accessed address.
For example, if the address most recently accessed (for READ instruction) is address “n”, and a current
address read operation is attempted, the data at address “n+1” is read.
In current address read operation, AK09916 generates an acknowledge after receiving a slave address for the
READ instruction (R/W bit = “1”). Next, AK09916 transfers the data specified by the internal address
counter starting with the next clock pulse, then increments the internal counter by one. If the master IC
generates a stop condition instead of an acknowledge after AK09916 transmits one byte of data, the read
operation stops.
S
S
T
O
P
T
A
R
T
R/W="1"
Slave
Address
Data(n+1)
Data(n+2)
Data(n+3)
Data(n+x)
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 10.8. Current Address READ
10.1.3.2. Random Address READ
By random address read operation, data at an arbitrary address can be read.
The random address read operation requires to execute WRITE instruction as dummy before a slave address
for the READ instruction (R/W bit = “1”) is transmitted. In random read operation, a start condition is first
generated then a slave address for the WRITE instruction (R/W bit = “0”) and a read address are transmitted
sequentially.
After AK09916 generates an acknowledge in response to this address transmission, a start condition and a
slave address for the READ instruction (R/W bit = “1”) are generated again. AK09916 generates an
acknowledge in response to this slave address transmission. Next, AK09916 transfers the data at the
specified address then increments the internal address counter by one. If the master IC generates a stop
condition instead of an acknowledge after data is transferred, the read operation stops.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Register
Address(n)
Slave
Address
Data(n)
Data(n+1)
Data(n+x)
S
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 10.9. Random Address READ
015007392-E-02
2015/12
- 18 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
