[AK09916]
10.1.1.3. Acknowledge
The IC that is transmitting data releases the SDA line (in the “High” state) after sending 1-byte data.
The IC that receives the data drives the SDA line to “Low” on the next clock pulse. This operation is referred
as acknowledge. With this operation, whether data has been transferred successfully can be checked.
AK09916 generates an acknowledge after reception of a start condition and slave address.
When a WRITE instruction is executed, AK09916 generates an acknowledge after every byte is received.
When a READ instruction is executed, AK09916 generates an acknowledge then transfers the data stored at
the specified address. Next, AK09916 releases the SDA line then monitors the SDA line. If a master IC
generates an acknowledge instead of a stop condition, AK09916 transmits the 8bit data stored at the next
address. If no acknowledge is generated, AK09916 stops data transmission.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
Figure 10.3. Generation of Acknowledge
10.1.1.4. Slave Address
The slave address of AK09916 is 0Ch.
MSB
LSB
0
0
0
1
1
0
0
R/W
Figure 10.4. Slave Address
The first byte including a slave address is transmitted after a start condition, and an IC to be accessed is
selected from the ICs on the bus according to the slave address.
When a slave address is transferred, the IC whose device address matches the transferred slave address
generates an acknowledge then executes an instruction. The 8th bit (least significant bit) of the first byte is a
R/W bit.
When the R/W bit is set to “1”, READ instruction is executed. When the R/W bit is set to “0”, WRITE
instruction is executed.
015007392-E-02
2015/12
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AKM [ ASAHI KASEI MICROSYSTEMS ]
