[AK09915]
9.Functional Descriptions
9.1. Power States
When VDD and VID are turned on from Vdd = OFF (0V) and Vid = OFF (0V), all registers in AK09915 are
initialized by POR circuit and AK09915 transits to Power-down mode.
All the states in the table below can be set, although the transition from state 2 to state 3 and the transition from
state 3 to state 2 are prohibited.
Table 9.1 Power States
State
VDD
VID
Power state
1
OFF (0V)
OFF (0V)
OFF (0V).
It doesn’t affect external interface. Digital input pins other than
SCL and SDA pin should be fixed to “L” (0V).
2
3
OFF (0V)
1.65V to 3.6V OFF (0V)
It doesn’t affect external interface.
OFF(0V)
1.7V to 3.6V
OFF (0V)
It doesn’t affect external interface. Digital input pins other than
SCL and SDA pin should be fixed to “L” (0V).
4
1.7V to 3.6V 1.65V to Vdd ON
9.2. Reset Functions
When the power state is ON, always keep Vid≤Vdd.
Power on Reset (POR) works until Vdd reaches to the operation effective voltage (about 1.1V: reference value
for design) on power-on sequence.
When Vdd = 1.7 to 3.6V, POR circuit and VID monitor circuit are active. When Vid = 0V, AK09915 is in reset
status and it consumes the current of reset state (IDD4).
AK09915 has four types of reset;
(1) Power on Reset (POR)
When Vdd rise is detected, POR circuit operates, and AK09915 is reset.
(2) VID monitor
When Vid is turned OFF (0V), AK09915 is reset.
(3) Reset pin (RSTN)
AK09915 is reset by Reset pin. When Reset pin is not used, connect to VID.
(4) Soft reset
AK09915 is reset by setting SRST bit.
After reset is completed, all registers and FIFO buffer are initialized and AK09915 transits to Power-down
mode automatically.
015006484-E-02
2016/7
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
