[AK09915]
High-speed mode (Hs-mode)
Cb≤100pF (Cb: load capacitance)
fSCLH≤2.5MHz
Symbol
fSCLH
tHIGH
tLOW
Parameter
Min.
Typ.
Max.
Unit
SCLH clock frequency
SCLH clock “High” time
SCLH clock “Low” time
SCLH rise time
2.5
MHz
ns
ns
110
220
10
tR_CL
40
80
ns
SCLH rise time after a repeated START
condition and after an acknowledge bit
tR_CL1
10
ns
tR_DA
tF_CL
tF_DA
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tSP
SDAH rise time
SCLH fall time
SDAH fall time
10
-
-
160
160
0
10
160
80
40
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
Start Condition hold time
Start Condition setup time
SDAH hold time (vs. SCLH falling edge)
SDAH setup time (vs. SCLH rising edge)
Stop Condition setup time
Noise suppression pulse width
10
Cb≤400pF
fSCLH≤1.7MHz
Symbol
fSCLH
tHIGH
tLOW
Parameter
Min.
Typ.
Max.
1.7
Unit
MHz
ns
ns
ns
SCLH clock frequency
SCLH clock “High” time
SCLH clock “Low” time
SCLH rise time
120
320
20
tR_CL
80
SCLH rise time after a repeated START
condition and after an acknowledge bit
tR_CL1
20
160
ns
tR_DA
tF_CL
tF_DA
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tSP
SDAH rise time
SCLH fall time
SDAH fall time
20
-
-
160
160
0
10
160
160
80
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
Start Condition hold time
Start Condition setup time
SDAH hold time (vs. SCLH falling edge)
SDAH setup time (vs. SCLH rising edge)
Stop Condition setup time
Noise suppression pulse width
10
015006484-E-02
2016/7
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
