HPMX-5002 Pin Description,
continued
No.
41
42
43
44
45
47
18,19,
36, 46,
48
Mnemonic
DC1B
VSUB
XLO
PLL
RX
BGR
N/C
I/O Type
Analog DC
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog DC
Not
connected
Description
External capacitor connection for decoupling IF limiting amplifier
Substrate connection
Controls bias to VCO and PLL components in conjunction with PLL pin
Controls bias to VCO and PLL components in conjunction with XLO pin
Controls bias to receive signal path, RSSI, data slicer
External capacitor connection for decoupling bandgap reference voltage
All unconnected pins should be connected to a low-noise ground
Table 1: HPMX-5002 Mode Control
Table 2: HPMX-5002 PLL Divider Programming
(CMOS Logic Levels)
Mode
PLL
TX
RX
STBY
“flywheel”
PLL
1
0
1
1
XLO
0
0
0
1
see text
RX
1
1
0
1
(CMOS Logic Levels)
REF divide by:
9
12
16
Not defined
LO2 divide by:
90
216
DIV1
1
0
0
1
X
X
DIV2
0
0
1
1
X
X
DIV3
X
X
X
X
0
1
7-110
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