HPMX-5002 Functional Block Diagram
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2
TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
OSCOP
90/216
OSCOPB
CHARGE
PUMP
φ
FREQ.
DET.
9/12/16
DIV1
LOCK
DET.
BIAS
CONTROL
REF
BGR
VCOADJ
VCOB
VCOA
DIV3
PFD
LKDET
PLL
RX
XLO
HPMX-5002 Absolute Maximum Ratings
[1]
Symbol
Parameter
V
CC
Supply Voltage
Voltage at any Pin
[4]
Power Dissipation
[2,3]
Junction Temperature
Storage Temperature
Units
V
V
mW
°C
°C
Min.
-0.2
-0.2
Max.
7.5
V
CC
+ 0.2
200
+110
+125
Thermal Resistance
[2]
:
θ
jc
= 80°C/W
Notes:
1. Operation of this device in excess
of any of these parameters may
cause permanent damage.
2. T
case
= 25°C
3. Derate at 10 mW/°C for T
case
> 90°C
4. Except CMOS logic inputs, see
Summary Characterization
Information Table.
P
diss
T
STG
-55
HPMX-5002 Guaranteed Electrical Specifications
Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < V
CC
< 5.5 V.
Test results are based upon use of networks shown in test diagram (see Figure 1). f
in
= 110.592 MHz.
Typical values are for V
CCX
= 3.0 V, T
A
= 25°C.
Symbol
Parameters and Test Conditions
Units
Min.
Typ.
Max.
I
ccx
Total V
ccx
supply current
(PLL locked)
(PLL locked)
RX mode
PLL mode
TX “flywheel” mode
Standby mode
high current mode
low current mode
input matched to 50
Ω
mA
mA
mA
µA
µA
µA
dB
21
16
9
400
30
5
550
50
8
27
20
11.5
100
1000
100
GIF1
VDATOP
VDATOP
Charge pump current
Charge pump current
Mixer power gain from
IP1 to IF1, external load
impedance of 600
Ω
Data slicer output level
Data slicer output level
Logic ‘0’
Logic ‘1’
V
V
0.3
V
ccx
-0.3
7-107
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
