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16910A 参数 Datasheet PDF下载

16910A图片预览
型号: 16910A
PDF下载: 下载PDF文件 查看货源
内容描述: 逻辑分析仪 [Logic Analyzer]
分类和应用:
文件页数/大小: 35 页 / 1054 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Agilent 16760A Specifications and Characteristics  
Agilent Technologies 16760A Supplemental Specifications* and Characteristics (continued)  
Synchronous State  
Analysis [4] (continued) 1.5 Gb/s mode  
1.25 Gb/s mode  
800 Mb/s mode  
400 Mb/s mode  
200 Mb/s mode  
Maximum trigger  
sequence levels  
2
2
4
16  
16  
Maximum trigger  
sequencer speed  
1.5 Gb/s  
Default  
N/A  
1.25 Gb/s  
Default  
N/A  
800 MHz  
Default  
N/A  
400 MHz  
Default  
N/A  
200 MHz  
Store qualification  
Default and per  
sequence level  
Maximum  
global counter  
16,777,215  
16,777,215  
32 bits [3]  
Maximum  
occurrence counter  
N/A  
N/A  
N/A  
N/A  
Maximum pattern/  
range term width  
32 bits [3]  
32 bits [3]  
32 bits [3]  
32 bits [3]  
Timer value range  
Timer resolution  
Timer accuracy  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
100 ns to 4397 seconds  
4 ns  
(10 ns ꢀ 0.01ꢁ of  
value)  
Timer reset latency  
N/A  
N/A  
N/A  
N/A  
65 ns  
Data in to BNC port  
out latency  
150 ns  
150 ns  
150 ns  
150 ns  
150 ns  
Flag set/reset to  
evaluation latency  
N/A  
N/A  
N/A  
N/A  
110 ns  
[1] In 1.25 Gb/s and 1.5 Gb/s modes, only the even-numbered channels (0, 2, 4, etc.) are acquired.  
[2] The resolution of the hardware used to assign time tags is 4 ns. Times of intermediate states are calculated.  
[3] Maximum label width is 32 bits. Wider patterns can be created by Anding” multiple labels together.  
[4] The choice of probe can limit system performance. Select a probe rated at the speed of the selected mode (or greater) to maintain system bandwidth.  
Asynchronous Timing Analysis  
Maximum timing analysis sample rate  
Number of channels  
Conventional Timing Analysis  
800 MHz  
Transitional Timing Analysis  
400 MHz  
34 x (number of modules)  
Sampling rates < 400 MHz: 34 x (number of modules)  
Sampling rates = 400 MHz:  
34 x (number of modules) – 17 [1]  
Maximum channels on a  
170 (5 modules)  
170 (5 modules)  
single time base and trigger  
Sample period  
Memory Depth  
1.25 ns  
2.5 ns to 1 ms [1]  
32 M Samples [1]  
64 M Samples  
[1] With all pods assigned in transitional/store qualified timing, minimum sample period is 5 ns and maximum memory depth is 16 M samples.  
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