T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
7 Transmission Superblock (continued)
7.6 DFAC Register Set
Table 22. DFCF: DFAC Configuration Register (0x05)
Reg
R/W
Bit 7
ILOSS
0
Bit 6
Bit 5
Bit 4
—
Bit 3
UOADS
1
Bit 2
Bit 1
Bit 0
DFCF
R/W
USIMRST URESET
ACT_ANSI AUTOEOC GRESET
RESET Default
0
0
0
0
1
0
Bit
Symbol
Name/Description
Insertion Loss Test Control. Causes the U-interface transmitter to continuously transmit the sequence
SN1. The U-interface transceiver remains reset during this mode.
7
ILOSS
0: No effect on device operation.
1: U transmitter sends SN1 tone continuously.
Special Simulation Reset for U-Block. This signal causes assertion of a special reset that is used for fac-
tory testing of the U block. This bit should always be programmed to 0.
6
5
USIMRST
URESET
0: No effect on device operation.
1: U-block simulation reset (nonlatching-value readback will always be 0).
U Transceiver Reset. Assertion of this bit halts U-interface data transmission and clears adaptive filter
coefficients. During URESET, the U transmitter produces 0 V. The microcontroller may use this bit to put
the U-interface in a quiet mode for maintenance as described in ANSI T1.601 Section 6.5. In addition, this bit
should be asserted whenever return loss and longitudinal balance measurements are being made on the
U-interface.
0: No effect on device operation.
1: U block is held in reset (nonlatching-value readback will always be 0).
Reserved. Program to 0.
—
4
3
UOADS
UOA Default State. During activation, the bits UOA_n and OOF_n become transparent at the same time (at
U-interface synchronization time), but UOA_n is filtered for three occurrences before being acted upon, and
hence, a direct transition to the UOA state is not possible. To satisfy this ETSI ETR 080 requirement, the
UOADS bit allows the NTN to default to the presynchronization value of UOA_n to 0. Upon synchronization,
if UOADS = 0 is received, a transition to the UOA state occurs, because the 3-time filtering criteria is satis-
fied. UOADS defaults to 1, meaning that U-only activation, at start-up, causes the U-interface to fully syn-
chronize and then a transition to the UOA state occurs. It is recommended that UOADS be programmed to 1.
ACT Mode Select. Controls the state of the transmitted ACT bit when an EOC loopback 2 (2B+D) is re-
quested. The loopback occurs automatically if AUTOEOC bit is set. Otherwise, bit U2BDLT must be set to 0.
0: ACT = 1 during loopback 2 after INFO3 is recognized at the S/T-interface (per ETSI ETR 080). The
data received by the NT is not looped back towards the LT until after ACT = 1 is received from the LT.
Prior to this time, 2B+D data toward the LT is all 1s.
2
ACT_ANSI
1: ACT = 0 during loopback 2 (per ANSI T1.601). The data received at the NT is looped back towards the
LT as soon as the 2B+D loopback is enabled.
Automatic EOC Processor Enable. Enables EOC state machine which implements EOC processing per
ETSI ETR 080 (see Section 7.3.1, EOC State Machine (EOCSM) for details on the EOC state machine oper-
ation). The EOC state machine only responds to the addresses 000 and 111 as valid addresses.
1
0
AUTOEOC
GRESET
0: EOC state machine disabled.
1: EOC state machine enabled.
Global Software Reset. Assertion of this bit resets all internal modules except the 80C32 to their default
states. U-macro adaptive filter coefficients are cleared. Since performing a GRESET also resets this bit to its
default state, it is not necessary to write it back to a 0 after writing a 1.
0: No effect on device operation.
1: Reset all circuitry except internal 80C32.
Lucent Technologies Inc.
33
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