T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
Similarly, the content of the U-interface downstream B1
channel is available to the microcontroller by reading
B1DN register 53h. The microcontroller can break the
normal data flow from U-interface to GCI, by writing
into the B1DN register the content it wants to be sent to
the GCI downstream B1 channel (assuming that
GCOF2[U_FORCE_B1DN] = DFR[B1_SEL] = 1 and
ECR0[LB1] = 0).
7 Transmission Superblock (continued)
7.3 Data Flow/Activation Control Module
(DFAC) (continued)
7.3.4 Data Flow Control
Figure 8 shows the high-level view of the 2B+D data
flow. The downstream buffer (DB) and upstream buffer
(UB) submodules control the downstream and
upstream paths, respectively.
The B1UP register (51h) and B1DN register (53h) are
both read/write registers. Hence, data can be read from
these registers and also written into them for transmit-
ting in the proper direction.
When the B-channel data flow is configured to be
between the U-interface and the GCI interface, the cor-
responding S/T-interface channel is disabled. The con-
verse is also true, i.e., when the data flow is between
the S- and U-interfaces, the corresponding GCI+ inter-
face channel is disabled. The D-channel packets are
never passed to the GCI interfaces.
The microcontroller can write into B2UP register 52h
the content it wants to be transferred on the U-interface
upstream B2 channel (assuming
DFR[U_FORCE_B2UP] = DFR[B2_SEL] = 1 and
ECR0[LB2] = 0).
Similarly, the content of the U-interface downstream B2
channel is available to the microcontroller by reading
B2DN register 54h. The microcontroller can break the
normal data flow from U-interface to GCI, by writing
into the B2DN register the content it wants to be sent to
the GCI downstream B2 channel (assuming that
GCOF2[U_FORCE_B2DN] = DFR[B2_SEL] = 1 and
ECR0[LB2] = 0).
All D-channel packets are passed to the S/T-interface.
The packets are passed to the HDLC module depend-
ing on the address recognition configuration, see Sec-
tion 9.3, HDLC Receiver.
GCI BLOCK
RX
TX
The following table summarizes the microcontroller
access to upstream and downstream B1 and B2 chan-
nels:
2B
DB
2B
RX
TX
TX
BxUP
BxDN
W
R
1
R
W
0
2B+D
2B+D
2B+D
LOOPBACK
S/T BLOCK
U BLOCK
U_FORCE
_BxUP
2B+D
UB
TX
RX
U_FORCE
_BxDN
0
1
D
D
Action
B-channels on the
U-interface are
B-channels on the GCI/
TDM registers are
RX
accessed. Upstream
registers are write
only, downstream reg- downstream registers
isters are read only. are write only.
accessed. Upstream
registers are read only,
HDLC BLOCK
5-6507F
Figure 8. 2B+D Data Flow Block Diagram
DFR[PFSx_ACT] and DFR[Bx_SEL] need to be set to
1 and ECR0[LBx] needs to be set to 0 in order to acti-
vate these functions.
7.4 Microcontroller Access to Upstream and
Downstream B1 and B2 Channels
7.5 LT Mode
The microcontroller can write into B1UP register 51h
the content it wants to be transferred on the U-interface
upstream B1 channel (assuming
DFR[U_FORCE_B1UP] = DFR[B1_SEL] = 1 and
ECR0[LB1] = 0). In this way, the microcontroller can
process the upstream GCI information (such as imple-
menting a bit-robbing algorithm on pair-gain applica-
tions).
The T9000 device can also be operated in LT mode.
Setting the register bit DOCR[NT_LT] to 1 changes the
T9000 from NT operational mode to LT operational
mode.
When the device is operating in LT mode, an 8 kHz
master transmit clock (MTC) must be provided as an
input on GPIO2.6.
32
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
