T7507 Quad PCM Codec with Filters,
Termination Impedance, and Hybrid Balance
Data Sheet
August 1999
Microprocessor Interface
Table 24. T7507 Microprocessor Interface Timing
Frequency of CCLK = 2.048 MHz.
Symbol
Parameter
Test Conditions
Min Max Unit
tCCLCCH Time of CCLK Low
tCCHCCL Time of CCLK High
tCCHCCH Period of CCLK
—
—
—
—
—
160
160
488
—
—
—
—
50
50
—
ns
ns
ns
ns
ns
ns
tCCH1CCH2 Rise Time of CCLK
tCCL1CCL2 Fall Time of CCLK
—
tCSLCCL
CSEL Low to CCLK Transition
Measured from first
CCLK low transition
50
tCCLCSH
CCLK Low to CSEL High
Measured from eighth
CCLK low transition
30
—
ns
tCIVCCL
tCCLCIX
tCSHCSL
tSU1BO2
tSU2BO1
tSU1RD
tSU2RD
tENL
Setup Time, Data Input/Output Valid to CCLK Low
Hold Time, CCLK Low to Data Input/Output Invalid
Minimum Time Between Writes
—
—
—
—
—
—
—
—
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
50
Setup Time for B0—B1 Data
488
488
488
488
977
Setup Time for B0—B1 Data
Setup Time for RD1, RD2, RD3 Data
Setup Time for RD1, RD2, RD3 Data
Enable Pulse Width
Lucent Technologies Inc.
23
AGERE [ AGERE SYSTEMS ]
