Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
The OR3C/T55 array in Figure 1 has PLCs arranged in
an array of 18 rows and 18 columns. The location of a
PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
located on all four sides of the FPGA between the
PLCs and the device edge. PICs are indicated using
PT and PB to designate PICs on the top and bottom
sides of the array, respectively, and PL and PR to des-
ignate PICs along the left and right sides of the array,
respectively. The position of a PIC on an edge of the
array is indicated by a number, counting from left to
right for PT and PB and top to bottom for PL and PR
PICs.
Description (continued)
ORCA Foundry Development System
The ORCA Foundry Development System is used to
process a design from a netlist to a configured FPGA.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two points
in the design flow: at design entry and at the bit stream
generation stage.
Each PIC contains routing resources and four program-
mable I/Os (PIOs). Each PIO contains the necessary
I/O buffers to interface to bond pads. PIOs in Series 3
FPGAs also contain input and output FFs, fast open-
drain capability on output buffers, special output logic
functions, and signal multiplexing/demultiplexing capa-
bilities.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter-
mine device speed and a back-annotated netlist can be
created to allow simulation. Timing and simulation out-
put files from ORCA Foundry are also compatible with
many third-party analysis tools. Its bit stream generator
is then used to generate the configuration data which is
loaded into the FPGA’s internal configuration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Com-
bined with the front-end tools, ORCA Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this data sheet.
PLCs comprise a programmable function unit (PFU), a
supplemental logic and interconnect cell (SLIC), and
routing resources. The PFU is the main logic element
of the PLC, containing elements for both combinatorial
and sequential logic. Combinatorial logic is done in
look-up tables (LUTs) located in the PFU. The PFU can
be used in different modes to meet different logic
requirements. The LUT’s twin-quad architecture pro-
vides a configurable medium-/large-grain architecture
that can be used to implement from one to eight inde-
pendent combinatorial logic functions or a large num-
ber of complex logic functions using multiple LUTs. The
flexibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
gate count per PFU while increasing system speed.
Architecture
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4- or 5-input
logic function and many multilevel logic functions using
ORCA’s softwired LUT (SWL) connections. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
The ORCA Series 3 FPGA comprises three basic ele-
ments: PLCs, PICs, and system-level functions. Figure
1 shows an array of programmable logic cells (PLCs)
surrounded by programmable input/output cells (PICs).
Also shown are the interquad routing blocks (hIQ, vIQ)
present in Series 3. System-level functions (located in
the corners of the array) and the routing resources and
configuration RAM are not shown in Figure 1.
Lucent Technologies Inc.
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