Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Page
Table of Contents
Page Contents
Contents
Explicit Mode ...........................................................90
Figure 54. Master Parallel Configuration Schematic 92
Figure 55. Master Serial Configuration Schematic ...93
Figure 56. Asynchronous Peripheral Configuration ..94
Figure 57. PowerPC/MPI Configuration Schematic ..95
Figure 58. i960/MPI Configuration Schematic ..........95
Figure 59. Configuration Through MPI .....................95
Figure 60. Readback Through MPI ..........................96
Figure 61. Slave Serial Configuration Schematic .....97
Figure 62. Slave Parallel Configuration Schematic ..97
Figure 63. Daisy-Chain Configuration Schematic .....98
Figure 64. Combinatorial PFU Timing ....................105
Figure 65. Synchronous Memory Write
Characteristics ......................................................109
Figure 66. Synchronous Memory Read Cycle ........110
Figure 67. MPI PowerPC User Space Read Timing 117
Figure 68. MPI PowerPC User Space Write Timing 117
Figure 69. MPI PowerPC Internal Read Timing .....118
Figure 70. MPI PowerPC Internal Write Timing ......118
Figure 71. MPI i960 User Space Read Timing .......119
Figure 72. MPI i960 User Space Write Timing .......119
Figure 73. MPI i960 Internal Read Timing ..............120
Figure 74. MPI i960 Internal Write Timing ..............120
Figure 75. Boundary-Scan Timing Diagram ...........122
Figure 76. ExpressCLK to Output Delay ................125
Figure 77. Fast Clock to Output Delay ...................126
Figure 78. System Clock to Output Delay ..............127
Figure 79. Input to ExpressCLK Setup/Hold Time ..129
Figure 80. Input to Fast Clock Setup/Hold Time .....131
Figure 81. Input to System Clock Setup/Hold Time 132
Figure 82. General Configuration Mode Timing
Diagram .................................................................135
Figure 83. Master Serial Configuration Mode
Timing Diagram .....................................................136
Figure 84. Master Parallel Configuration Mode
Timing Diagram .....................................................137
Figure 85. Asynchronous Peripheral Configuration
Mode Timing Diagram ...........................................138
Figure 86. Slave Serial Configuration Mode
Timing Diagram .....................................................139
Figure 87. Slave Parallel Configuration Mode
Timing Diagram .....................................................140
Figure 88. Readback Timing Diagram ....................142
Figure 89. ac Test Loads ........................................143
Figure 90. Output Buffer Delays .............................143
Figure 91. Input Buffer Delays ................................143
Figure 92. Sinklim (TJ = 25 °C, VDD = 5.0 V) ..........144
Figure 93. Slewlim (TJ = 25 °C, VDD = 5.0 V) .........144
Figure 94. Fast (TJ °C, VDD = 5.0 V) ......................144
Figure 95. Sinklim (TJ = 125 °C, VDD = 4.5 V) ........144
Figure 96. Slewlim (TJ = 125 °C, VDD = 4.5 V) .......144
Figure 97. Fast (TJ = 125 °C, VDD = 4.5 V) ............144
Figure 98. Sinklim (TJ = 25 °C, VDD = 3.3 V) ..........145
Figure 99. Slewlim (TJ = 25 °C, VDD = 3.3 V) .........145
Figure 100. Fast (TJ = 25 °C, VDD = 3.3 V) ............145
Figure 101. Sinklim (TJ = 125 °C, VDD = 3.0 V) ......145
Figure 102. Slewlim (TJ = 125 °C, VDD = 3.0 V) .....145
Figure 103. Fast (TJ = 125 °C, VDD = 3.0 V) ..........145
Figure 104. Package Parasitics ..............................196
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