Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Initialization
FPGA States of Operation
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are configured based on the con-
figuration mode, as determined by the mode select
inputs M[2:0]. A time-out delay is initiated when VDD
reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txxx) to allow the power supply voltage to
stabilize. The INIT and DONE outputs are low. At pow-
erup, if VDD does not rise from 2.0 V to VDD in less than
25 ms, the user should delay configuration by inputting
a low into INIT, PRGM, or RESET until VDD is greater
than the recommended minimum operating voltage
(4.75 V for OR3Cxx commercial devices and 3.0 V for
OR3Txxx devices).
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, configura-
tion, and start-up. Figure 49 outlines these three FPGA
states.
POWERUP
– POWER-ON TIME DELAY
INITIALIZATION
– CLEAR CONFIGURATION
MEMORY
– INIT LOW, HDC HIGH, LDC LOW
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
YES
NO
NO
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
CONFIGURATION
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME
WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
RESET
OR
PRGM
LOW
START-UP
PRGM
LOW
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
OPERATION
5-4529(F)
Figure 49. FPGA States of Operation
The high during configuration (HDC), low during config-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
Lucent Technologies Inc.
85
AGERE [ AGERE SYSTEMS ]
