Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Reconfiguration
FPGA States of Operation (continued)
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM. The con-
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfigu-
ration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.
CCLK_NOSYNC
F
DONE
C1
C1
C2
C2
C3
C3
C4
C4
I/O
Partial Reconfiguration
GSRN
ACTIVE
C1
C2
C3
C4
All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
CCLK_SYNC
DONE IN
DONE
F
Di + 4
Di + 4
C1, C2, C3, OR C4
I/O
Di Di + 1
Di Di + 1
Di + 2
Di + 2
Di + 3
Di + 3
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
GSRN
ACTIVE
UCLK
UCLK_NOSYNC
F
DONE
I/O
C1
U1
U2
U2
U3
U4
U4
Other Configuration Options
U1
U1
U3
U3
GSRN
ACTIVE
There are many other configuration options available to
the user that can be set during bit stream generation in
ORCA Foundry. These include options to enable
boundary scan and/or the microprocessor interface
(MPI) and/or the programmable clock manager (PCM),
readback options, and options to control and use the
internal oscillator after configuration.
U2
U4
UCLK_SYNC
DONE IN
DONE
I/O
F
C1
U1, U2, U3, OR U4
Di Di + 1
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ORCA Foundry documenta-
tion.
Di + 2
Di + 3
Di + 3
Di + 4
GSRN
ACTIVE
Di Di + 1
Di + 2
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
Note: F = finished, no more CLKs required.
5-2761(F)
Figure 51. Start-Up Waveforms
88
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
