Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
Table 31. PCM Control Registers (continued)
Bit #
Function
Bits [5:4]
ExpressCLK Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: divided (DIV2) delay line output
Bits [7:6]
System Clock Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: reserved
Register 7—PCM Control Programming
Bit 0
Bit 1
Bit 2
PCM Analog Power Supply Switch. 1 = power supply on, 0 = power supply off.
PCM Reset. A value of 1 resets all PCM logic for PLL and DLL modes.
DLL Reset. A value of 1 resets the clock generation logic for DLL mode. No dividers or user reg-
isters are affected.
Bits [5:3]
Bit 6
Reserved.
PCM Configuration Operation Enable Bit. 0 = normal configuration operation. During configu-
ration (DONE = 0), the PCM analog power supply will be off, the PCM output data bus is 3-stated,
and the LOCK signal is asserted to logic 0. The PCM will power up when DONE = 1.
1 = PCM operation during configuration. The PCM may be powered up (see bit 0) and begin
operation, or continue operation. The setup of the PCM can be performed via the configuration
bit stream.
Bit 7
PCM GSRN Enable Bit. 0 = normal GSRN operation. 1 = GSRN has no effect on PCM logic, so
clock processing will not be interrupted by a chip reset. Default is 0.
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