Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
D[7:0]
D[7:0]
TDI
TDO
TDI
TDO
TDO
ORCA
SERIES
FPGA
ORCA
SERIES
FPGA
LUCENT
BOUNDARY-
SCAN
MASTER
CE
TMS0
TCK
TMS
TCK
TMS
TCK
MICRO-
PROCESSOR
(DUT)
(DUT)
RA
R/W
DAV
INT
SP
(BSM)
TDI
INTR
TDI
TDO
ORCA
SERIES
FPGA
TMS
TCK
(DUT)
5-6765(F)
Figure 37. Boundary-Scan Interface
Table 13. Boundary-Scan Instructions
The boundary-scan support circuit shown in Figure 37
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conver-
sion, as well as three 8K data buffers. The BSM also
increases test throughput with a dedicated automatic
test-pattern generator and with compression of the test
response with a signature analysis register. The PC-
based boundary-scan test card/software allows a user
to quickly prototype a boundary-scan test setup.
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
PLC Scan Ring 1 (PSR1)/USERCODE
RAM Write (RAM_W)
IDCODE
SAMPLE/PRELOAD
PLC Scan Ring 2 (PSR2)
RAM Read (RAM_R)
BYPASS
Boundary-Scan Instructions
The ORCA Series boundary-scan circuitry is used for
three mandatory IEEE 1149.1/D1 tests (EXTEST,
SAMPLE/PRELOAD, BYPASS), the optional IEEE
1149.1/D1 IDCODE instruction, and five ORCA-defined
instructions. The 3-bit wide instruction register sup-
ports the nine instructions listed in Table 13, where the
use of PSR1 or USERCODE is selectable by a bit
stream option.
58
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
