Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
s
TMS TDI
TCK
TDO
TMS TDI
TCK
Boundary Scan
net a
TDO
net b
U2
U2
net c
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the IEEE standard 1149.1/D1 (IEEE Standard
Test Access Port and Boundary-Scan Architecture) is
implemented in the ORCA series of FPGAs. It allows
users to efficiently test the interconnection between
integrated circuits on a PCB as well as test the inte-
grated circuit itself. The IEEE 1149.1/D1 standard is a
well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
TDI
TMS
TCK
TDO
TMS TDI
TCK
TDO
TMS TDI
TCK
TDO
U3
U4
SEE ENLARGED VIEW BELOW
The IEEE 1149.1/D1 standard defines a test access
port (TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The ORCA Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and test data out
(TDO). The PRGM pin used to reconfigure the device
also resets the boundary-scan logic.
TDO TCK TMS TDI
TAPC
PT[ij]
BSC
BDC DCC
SCAN
IN
SCAN
OUT
BYPASS
REGISTER
INSTRUCTION
REGISTER
p_in
p_ts
p_out
SCAN
OUT
SCAN
IN
p_ts
PR[ij]
BSC
DCC
p_in
BSC
BDC
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 36, where boundary scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
PLC
ARRAY
p_out
p_in
p_out
p_ts
BDC
DCC
PL[ij]
SCAN
IN
SCAN
OUT
p_out
p_ts
p_in
BSC
DCC BDC
SCAN
OUT
SCAN
IN
PB[ij]
5-5972(F)
Key: BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry
Figure 37 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Lucent Technologies Inc.
57
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