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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Contents  
Table of Contents  
Page Contents  
Page  
Features ......................................................................1  
System-Level Features................................................6  
Description...................................................................7  
FPGA Overview ........................................................7  
PLC Logic ..................................................................7  
PIC Logic ...................................................................8  
System Features .......................................................8  
Routing ......................................................................8  
Configuration .............................................................8  
ORCA Foundry Development System ......................9  
Architecture .................................................................9  
Programmable Logic Cells ........................................11  
Programmable Function Unit ..................................11  
Look-Up Table Operating Modes ............................13  
Supplemental Logic and Interconnect Cell (SLIC) ..21  
PLC Latches/Flip-Flops ...........................................25  
PLC Routing Resources ..........................................27  
PLC Architectural Description .................................34  
Programmable Input/Output Cells .............................36  
5 V Tolerant I/O .......................................................37  
PCI Compliant I/O ...................................................37  
Inputs ......................................................................38  
Outputs ....................................................................41  
PIC Routing Resources ...........................................44  
PIC Architectural Description ..................................45  
High-Level Routing Resources..................................47  
Interquad Routing ....................................................47  
Programmable Corner Cell Routing ........................48  
PIC Interquad (MID) Routing ...................................49  
Clock Distribution Network ........................................50  
PFU Clock Sources .................................................50  
Clock Distribution in the PLC Array .........................51  
Clock Sources to the PLC Array .............................52  
Clocks in the PICs ...................................................52  
ExpressCLK Inputs .................................................53  
Selecting Clock Input Pins ......................................53  
Special Function Blocks ............................................54  
Single Function Blocks ............................................54  
Boundary Scan ........................................................57  
Microprocessor Interface (MPI) .................................64  
PowerPC System ....................................................65  
i960 System ............................................................66  
MPI Interface to FPGA ............................................67  
MPI Setup and Control ............................................68  
Programmable Clock Manager (PCM) ......................72  
PCM Registers ........................................................73  
Delay-Locked Loop (DLL) Mode .............................75  
Phase-Locked Loop (PLL) Mode ............................76  
PCM/FPGA Internal Interface .................................79  
PCM Operation .......................................................79  
PCM Detailed Programming ...................................80  
PCM Applications ....................................................83  
PCM Cautions ........................................................ 84  
FPGA States of Operation........................................ 85  
Initialization ............................................................. 85  
Configuration .......................................................... 86  
Start-Up .................................................................. 87  
Reconfiguration ...................................................... 88  
Partial Reconfiguration ........................................... 88  
Other Configuration Options ................................... 88  
Configuration Data Format ...................................... 89  
Using ORCA Foundry to Generate  
Configuration RAM Data ....................................... 89  
Configuration Data Frame ...................................... 89  
Bit Stream Error Checking ...................................... 91  
FPGA Configuration Modes...................................... 92  
Master Parallel Mode ............................................. 92  
Master Serial Mode ................................................ 93  
Asynchronous Peripheral Mode ............................. 94  
Microprocessor Interface (MPI) Mode .................... 94  
Slave Serial Mode .................................................. 97  
Slave Parallel Mode ............................................... 97  
Daisy-Chaining ....................................................... 98  
Daisy-Chaining with Boundary Scan ...................... 99  
Absolute Maximum Ratings.................................... 100  
Recommended Operating Conditions .................. 100  
Electrical Characteristics ........................................ 101  
Timing Characteristics............................................ 103  
Description ........................................................... 103  
PFU Timing ......................................................... 104  
PLC Timing ........................................................... 111  
SLIC Timing .......................................................... 111  
PIO Timing ........................................................... 112  
Special Function Blocks Timing ........................... 115  
Clock Timing ......................................................... 123  
Configuration Timing ............................................ 133  
Readback Timing ................................................. 142  
Input/Output Buffer Measurement Conditions ........ 143  
Output Buffer Characteristics ................................. 144  
OR3Cxx ................................................................ 144  
OR3Txxx .............................................................. 145  
Estimating Power Dissipation................................. 146  
OR3Cxx ................................................................ 146  
OR3Txxx (Preliminary Information) ...................... 147  
Pin Information ....................................................... 149  
Pin Descriptions ................................................... 149  
Package Compatibility .......................................... 153  
Compatibility with OR2C/TxxA Series .................. 154  
Package Thermal Characteristics........................... 194  
ΘJA ....................................................................... 194  
ψ
JC ...................................................................... 194  
ΘJC ...................................................................... 194  
ΘJB ...................................................................... 194  
FPGA Maximum Junction Temperature ............... 195  
Lucent Technologies Inc.  
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