LU6612
Data Sheet
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
Name
Parameter
RX/RY Activity to CRS Assertion
RX/RY Activity to RX_CLK Valid
IDL to CRS Deassertion
Min
Max
Unit
t15
t16
t17
t18
40
500
2300
550
ns
ns
ns
ns
800
200
400
Dead Signal to CRS Deassertion
1000
(RECEIVE—DEAD SIGNAL)
(NOT IDL)
(RECEIVE—START OF PACKET)
(RECEIVE—END OF PACKET)
IDL
RX/RY
CRS
t18
t15
t17
RX_CLK
t16
5-5293(F).mr1
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
Name
Parameter
Min
Max
Unit
t19
t20
t21
t22
t23
TX_EN Asserted to Transmit Pair Activity
TX_EN Asserted to CRS Asserted Due to Internal Loopback
TX_EN Asserted to RX_CLK Valid Due to Internal Loopback
TX_EN Deasserted to IDL Transmission
IDL Pulse Width
50
5
1000
50
400
1900
1700
300
ns
ns
ns
ns
ns
250
350
(TRANSMIT—START OF PACKET)
(TRANSMIT—END OF PACKET)
TX_EN
TX/TY
CRS
IDL
t23
t19
t22
t20
RX_CLK
t21
5-5293(F).nr1
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
Lucent Technologies Inc.
28
AGERE [ AGERE SYSTEMS ]
