LU6612
Data Sheet
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 26. MII Data Timing (25 pF Load)
Name
Parameter
Min
Typ
Max
Unit
t1
t2
RXD[3:0], RX_ER, RX_DV, Valid to RX_CLK High
RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid
RX_CLK High
10/100
10/100
14/180
14/180
—
—
—
—
—
40
—
—
40
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t3
26/220
26/220
—
t4
RX_CLK Low
t5
RX_CLK Period
t6
TX_CLK High
14/180
14/180
—
26/220
26/220
—
t7
TX_CLK Low
t8
TX_CLK Period
t9
TXD[3:0], TX_EN, TX_ER, Setup to TX_CLK
TXD[3:0], TX_EN, TX_ER, Hold to TX_CLK
TXD[3:0], TX_EN, TX_ER Setup to LSCLK*
TXD[3:0], TX_EN, TX_ER, Hold to LSCLK*
15/140
0/0
—
t10
t11
t12
t13
—
10
—
0
—
First Bit of J on RX/RY While Transmitting Data to COL
Assert (half-duplex mode)
—
170
t14
First Bit of T Received on RX/RY While Transmitting to COL
Deasserted (half-duplex mode)
—
—
210
ns
* 100 Mbits/s only.
26
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
