Table 6. Interrupt Vector Sources, Locations, and Priorities
Interrupt
Priority1
(0 is the
Lowest
PTS
Vector
Location
Number
Interrupt Vector
Source(s)
Vector
Location
Priority)
Special
Unimplemented
Opcode
Unimplemented Opcode
2012h
N/A
N/A
Special
INT 15
Software Trap
Software Trap
NMI
2010h
203Eh
N/A
N/A
N/A
15
NMI2
INT 14
INT 13
HSI FIFO Full
HSI FIFO Full
Port 2.2
203Ch
203Ah
205Ch
205Ah
14
13
EXTINT 12
INT 12
INT 11
Timer 2 Overflow
Timer 2 Overflow
Timer 2 Capture
2038h
2036h
2058h
2056h
12
11
Timer 2 Capture2
HSI FIFO 4
INT 10
HSI FIFO
2034h
2054h
10
Fourth Entry
RI Flag3
INT 9
INT 8
INT 7
INT 6
Receive
2032h
2030h
200Eh
200Ch
2052h
2050h
204Eh
204Ch
9
8
7
6
TI Flag3
Transmit
EXTINT2
Serial Port
Port 2.2 or Port 0.7
RI Flag and
TI Flag4
INT 5
Software Timer
HSI.02
Software Timer 0-3
Timer 2 Reset
200Ah
204Ah
5
INT 4
INT 3
HSI.0 Pin
2008h
2006h
2048h
2046h
4
3
High Speed
Outputs
Events on HSO.0 thru
HSO.5 Lines
INT 2
INT 1
INT 0
HSI Data Available
EDAC Bit Error
Timer Overflow
HSI FIFO Full or
HSI Holding Reg.
Loaded
2004h
2002h
2000h
2044h
2042h
2040h
2
1
0
Single Bit Error
Single Bit Error OVF
Double Bit Error
Timer 1 or Timer 2
All of the previous maskable interrupts can be assigned to the PTS.
Any PTS interrupt has priority over all other maskable interrupts.
4
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
