Table 10: 68-lead Flat Pack Pin Descriptions
QFP Pin#
I/O
Name
Active
Description
612
TUO
RD
Low
Read. The RD signal is an output to external memory that is
only asserted during external memory reads.
622
TUO
ALE
High
Address Latch Enable. The ALE signal is an output to external
memory that is only asserted during external memory accesses.
ALE is used to specify that valid address information is avail-
able on the address/data bus, and signals the start of a bus cycle.
ALE is used by an external latch to demultiplex the address from
the address/data bus. Setting CCR.3 = 1 enables the ALE func-
tion of pin 62.
TUO
ADV
Low
Address Valid. The ADV signal is an output to external mem-
ory that is only asserted during external memory accesses. ADV
is driven high to specify that valid address information is avail-
able on the address/data bus. The ADV signal is held low during
the data transfer portion of the bus cycle, and is driven high
when the bus cycle completes. ADV is used by an external latch
to demultiplex the address from the address/data bus. Setting
CCR.3 = 0 enables the ADV function of pin 62.
63
64
TDO
INST
High
Instruction Fetch. The INST signal indicates the type of external
memory cycle being performed. The INST signal will be high
during instruction fetches, and will be low for data fetches.
Note: CCB bytes and Interrupt vectors are considered data.
TI
BUSWIDTH
---
Bus Width. The BUSWIDTH pin dynamically modifies the
width of bus cycles. When a high logic value is supplied, the
bus width will be set to 16-bits wide. When a low logic level is
supplied, the bus width will be set to 8-bits wide.
Setting CCR.1 = 1 enables the BUSWIDTH pin. Setting
CCR.1 = 0 disables the BUSWIDTH pin. As a result, the
UT80CRH196KD will only perform 8-bit wide bus cycles.
65
66
TUO
GND
CLKOUT
---
---
Clock Output. The CLKOUT signal is the output of the internal
clock. This signal has a 50% duty cycle, and runs at 1/2 the fre-
quency of the system clock input to XTAL1. Setting IOC3.1 = 0
will enable the CLKOUT output signal.
3
Digital circuit ground (0V). Recommended connection for sig-
nal integrity improvement. There are 4 other VSS pins, all of
VSS
which must be connected.
67
68
CI
XTAL1
VSS
---
---
External oscillator or clock input to the UT80CRH196KD. The
XTAL1 input is fed to the on-chip clock generator.
GND
Digital circuit ground (0V). There are 4 VSS pins, all of which
must be connected and one additional recomended VSS connec-
tion.
Notes:
1. These pins should be pulled high or low when using EDAC (i.e. EDACEN = 0) to prevent the voltages on these pins from floating to the switching threshold of
the input buffers during long read cycles.
2. These pins must be high on the rising edge of RESET in order to avoid entering any test modes.
3. This pin is a recommended V connection. The remaining 4 V pins are required to be tied to the circuit card ground plane.
SS
SS
22
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
