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CT1496-2 参数 Datasheet PDF下载

CT1496-2图片预览
型号: CT1496-2
PDF下载: 下载PDF文件 查看货源
内容描述: CT1496-2 MIL -STD - 1397型E 10MHz的低电平的串行曼彻斯特32位编码器 [CT1496-2 MIL-STD-1397 Type E 10MHz Low Level Serial Manchester 32 Bit Encoder]
分类和应用: 电信集成电路光电二极管编码器
文件页数/大小: 9 页 / 93 K
品牌: AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
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DC Electrical Characteristics (con’t)  
(VDD = 5V 10ꢀ, TC = -55 °C to +100°C, unless otherwise specified)  
SYMBOL  
PARAMETER  
LIMIT  
Sync Bit, WI Bit, 4 Bit SIS / SOS Input & 32 Bit Parallel Word Input  
IIH  
IIL  
Logic High Input Current  
20µA max @ VIH = 2.5V  
-400µA max @ VIL = 0.5V  
Logic Low Input Current 3/  
DC Supply Currents  
VCC = +5.5V (pin 31), all other pins at GND  
ICC  
590mA max  
Notes:  
1/ and 2/ The total loads on these outputpairs (1 & 2) must be matched to within 15pF in order to  
maintain signal skews between the lines of < 5nSec maximum.  
3/ Current out of a terminal is given as a negative value.  
4/ Maximum total capacitance loads allowable on these pins are:  
DATA, DATA  
TX INHIBIT  
DATAst & DATAst  
40 pF max  
45 pF max  
50 pF max  
AC Electrical Characteristics  
(VCC = 5V 10ꢀ, TC = -55 °C to +100°C, See Figure 1, unless otherwise specified)  
Symbol  
Parameter / Condition  
Min Max Unit  
T1  
T2  
Stable input data setup time prior to Sys Clr / Load rising edge  
Stable input data hold time after Sys Clr / Load rising edge  
Sys Clr / Load pulsewidth  
40  
20  
50  
40  
100  
30  
50  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
PW1  
T3  
Sys Clr / Load disable to Encoder Enable pulse  
Encoder Enable pulsewidth  
-
PW2  
T4  
400  
140  
-
Encoder Enable rising edge to TX Inhibit disable (thruput delay)  
Transmit / Self Test selection to TX Inhibit disable set-up time  
T5  
T6  
TX Inhibit disable to output data delay  
(Transmit / Self Test = high)  
10  
T7  
DATA Output to DATA output delay  
{ZLOAD (DATA) = ZLOAD (DATA), CLOAD < 40pF}  
-
5
ns  
PW3  
PW4  
T8  
DATA and DATA output half-bit pulsewidth  
DATA and DATA output bit pulsewidth  
TX Inhibit disable to output DATAST delay  
47  
97  
-
53  
103  
10  
5
ns  
ns  
ns  
ns  
T9  
DATAST output DATAST output delay  
{ZLOAD (DATAST) = ZLOAD (DATAST), CLOAD < 50pF}  
-
PW5  
PW6  
T10  
DATAST and DATAST output half-bit pulsewidth  
47  
97  
-
53  
103  
10  
-
ns  
ns  
ns  
ns  
DATAST and DATAST output bit pulsewidth  
End of output DATA, DATA, DATAst or DATAst to TX Inhibit enable  
TX Inhibit enable to next Transmit / Self Test selection  
T11  
50  
4
Aeroflex Circuit Technology  
SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700