40MHz
Parallel
OUTPUT LOGIC STATE TRUTH TABLE
OUTPUT STATES
Input Data (DBN)
CONDITIONS
Bit 1
TX INH (29) TX/ST (37) DATA (39) DATA (38) DATAst (33) DATAst (32)
Bit 2
Bit 3
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
(DBn)
HIGH
(DBn)
(DBn)
LOW
(DBn)
LOW
Bit 3
T1
T2
System
Clear / Load
PW1
T3
PW2
Encoder Enable
T4
TX Inhibit
Transmit /
Self Test
T5
T8
T11
T10
T7
PW4
DATA
DATA
T6
PW3
T10
T10
T9
DATAst
DATAst
PW6
PW5
T10
Output
Output
Output
Output
Data Bit 1 Data Bit 2 Data Bit 3
Data Bit N
Example
= 1
Example
= 1
Example
= 1
Example
= 0
Figure 1 – Encoder Timing Waveforms