OP467
WAFER TEST LIMITS
@ V
S
= ±15.0 V, T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current
1
Symbol
V
OS
I
B
I
OS
CMRR
PSRR
A
VO
V
O
I
SY
Conditions
V
CM
= 0 V
V
CM
= 0 V
V
CM
= ±12 V
V = ±4.5 V to ±18 V
R
L
= 2 kΩ
R
L
= 2 kΩ
V
O
= 0 V, R
L
= ∞
Limit
±0.5
600
100
±12
80
96
83
±13.0
10
Unit
mV max
nA max
nA max
V min/max
dB min
dB min
dB min
V min
mA max
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2
Guaranteed by CMR test.
Rev. F | Page 5 of 20
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