OP15/OP17–SPECIFICATIONS
؇
(@ V = ؎15 V, T = 25 C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
OP15A, OP15E
OP17A, OP17E
OP15F
OP17F
Typ
OP15G
OP17G
Typ
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Max
Min
Max Unit
Input Offset Voltage VOS
RS = 50 W
0.2
0.5
0.4
1.0
0.5
3.0
mV
Input Offset Current IOS
OP15
T J = 25∞C1
3
5
3
5
10
22
10
25
6
10
6
20
40
20
50
12
20
12
20
50
100
50
pA
pA
pA
pA
Device Operating
OP17
T J = 25∞C1
Device Operating
10
125
Input Bias Current
OP15
IB
T J = 25∞C1
±15
±18
±15
±20
±50
±30
±40
±30
±40
±100
±200
±100
±250
±60
±80
±60
±80
±200 pA
±400 pA
±200 pA
±500 pA
Device Operating
±110
±50
OP17
T J = 25∞C1
Device Operating
±130
Input Resistance
RIN
1012
1012
1012
W
Large-Signal
Voltage Gain
AVO
RL ≥ 2 kW
VO = ±10 V
100
240
75
220
50
200
V/mV
Output Voltage
Swing
VO
RL = 10 kW
RL = 2 kW
±12
±11
±13
±12.7
±12
±11
±13
±12.7
±12
±11
±13
±12.7
V
V
Supply Current
Slew Rate2
ISY
OP15
OP17
2.7
4.6
4.0
7.0
2.7
4.6
4.0
7.0
2.8
4.8
5.0
8.0
mA
mA
SR
AVCL = 1, OP15
AVCL = 5, OP17
10
45
13
60
7.5
35
11
50
5
25
9
40
V/ms
V/ms
Gain Bandwidth3
Product
GBW
CLBW
tS
OP15
OP17
4.0
20
6.0
30
3.5
15
5.7
28
3.0
11
5.4
26
MHz
MHz
Closed-Loop
Bandwidth
AVCL = 1, OP15
AVCL = 5, OP17
14
11
13
10
12
9
MHz
MHz
Settling T ime
OP15
T o 0.01%
T o 0.05%
T o 0.10%
T o 0.01%
T o 0.05%
T o 0.10%
4.5
1.5
1.2
1.5
0.7
0.6
4.5
1.5
1.2
1.5
0.7
0.6
4.7
1.6
1.3
1.6
0.8
0.7
ms
ms
ms
ms
ms
ms
OP17
Input Voltage Range IVR
±10.5
±10.5
±10.3
V
Common-Mode
Rejection Ratio
CMRR
VCM = ±10.5 V
VCM = ±10.3 V
86
100
10
86
100
10
dB
dB
82
96
10
Power Supply
Rejection Ratio
PSRR
en
VS = ±10 V to ±18 V
VS = ±10 V to ±18 V
51
51
mV/V
mV/V
80
Input Noise
Voltage Density
fO = 100 Hz
fO = 1 kHz
20
15
20
15
20
15
nV/÷Hz
nV/÷Hz
Input Noise
Current Density
in
fO = 100 Hz
fO = 1 kHz
0.01
0.01
0.01
0.01
0.01
0.01
pA/÷Hz
pA/÷Hz
Input Capacitance
NOT ES
CIN
3
3
3
pF
1Input bias current is specified for two different conditions. T he T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. T he warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus T J and IB versus T A. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
2Settling time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltages at the inverting input pit
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.
3Sample tested.
4Settling time is defined here for AV = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
–2–
REV. A
ADI [ ADI ]
