AD5940
Data Sheet
Bits
14
Bit Name
WAVEGENEN
Settings Description
Waveform generator enable. This bit enables the waveform generator.
Reset Access
0x0
R/W
0
Waveform generator disabled. The waveform generator includes a sinusoid
wave and a trapezoid wave.
1
Waveform generator enabled.
13
12
TEMPCONVEN
ADC temperature sensor convert enable. This bit enables the temperature
reading. If this bit is set to 1, a temperature reading is initiated. When the
temperature conversion is complete, the result available in the TEMPSENSDAT
register.
Temperature reading disabled.
Temperature reading enabled.
ADC temperature sensor channel enable. This bit enables the temperature sensor.
Temperature sensor disabled. The temperature sensor is powered down.
Temperature sensor enabled. The temperature sensor is powered up.
Temperature readings are not performed unless TEMPCONVEN = 1.
0x0
R/W
0
1
TEMPSENSEN
0x0
R/W
0
1
11
10
TIAEN
High speed TIA enable. This bit enables the high speed TIA.
High speed TIA disabled.
High speed TIA enabled.
0x0
0x0
R/W
R/W
0
1
INAMPEN
Excitation instrumentation amplifier enable. This bit enables the instrumentation
amplifier.
0
1
Programmable instrumentation amplifier disabled.
Programmable instrumentation amplifier enabled.
9
EXBUFEN
Excitation buffer enable. This bit enables the excitation buffer to drive the
resistance being measured.
0x0
R/W
0
1
Excitation buffer disabled.
Excitation buffer enabled.
8
7
ADCCONVEN
ADCEN
ADC conversion start enable.
ADC idle. The ADC is powered on, but is not converting.
ADC conversions enabled.
ADC power enable. This bit enables the ADC.
ADC disabled. The ADC is powered off.
ADC enabled. The ADC is powered on. The ADCCONVEN bit must be set to 1 to
start conversions.
0x0
0x0
R/W
R/W
0
1
0
1
6
DACEN
High speed DAC enable. This bit enables the high speed DAC, the corresponding
reconstruction filter, and the attenuator. This bit only enables the analog block
and does not include the DAC waveform generator.
0x0
R/W
0
1
High speed DAC disabled.
High speed DAC enabled.
5
HSREFDIS
Reserved
High speed reference disable. This bit is the power-down signal of the high
power reference. Set this bit to 1 to power down the reference.
High power reference enabled.
High power reference disabled.
Reserved.
0x0
0x0
R/W
R
0
1
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Rev. 0 | Page 24 of 130
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