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DAC8562FS 参数 Datasheet PDF下载

DAC8562FS图片预览
型号: DAC8562FS
PDF下载: 下载PDF文件 查看货源
内容描述: +5伏,并行输入完整的12位DAC [+5 Volt, Parallel Input Complete 12-Bit DAC]
分类和应用:
文件页数/大小: 16 页 / 638 K
品牌: ADI [ ADI ]
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DAC8562  
DAC8562 – M68HC11 Interface Program Source Code  
*
DAC8562–M68HC11 Interface Program Source Code (Continued)  
* Update DAC output with contents of input registers  
* DAC8562 to M68HC11 Interface Assembly Program  
*
* Adolfo A. Garcia  
* September 14, 1992  
*
DUMP  
*
BCLR PORTC,Y $02  
BSET PORTC,Y $02  
Assert CE/  
Latch DAC register  
* M68HC11 Register definitions  
*
PULA  
PULY  
PULX  
RTS  
When done, restore registers X, Y & A  
** Return to Main Program **  
PORTB  
PORTC  
*
EQU  
EQU  
$1004  
$1003  
Port C control register  
“0,0,0,0;0,CLR/,CE/,MSB-LSB/”  
Port C data direction  
DDRC  
*
EQU  
$1007  
* RAM variables:  
MSBS are encoded from 0 (Hex) to F (Hex)  
LSBS are encoded from 00 (Hex) to F (Hex)  
DAC requires two 8-bit loads  
*
*
*
MSBS  
LSBS  
EQU  
EQU  
$00  
$01  
Hi-byte: “0,0,0,0;MSB,DB10,DB9,DB8”  
Lo-byte: “DB7,DB6,DB5,DB4;DB3,DB2,  
DB1,DB0”  
*
* Main Program  
*
ORG  
LDS  
$C000  
#$CFFF  
Start of user’s RAM in EVB  
Top of C page RAM  
INIT  
*
* Initialize Port C Outputs  
*
LDAA #$07  
STAA DDRC  
0,0,0,0;0,1,1,1  
CLR/,CE/, and MSB-LSB/ are now enabled  
as outputs  
LDAA #$06  
0,0.0,0;0,1,1,0  
*
CLR/-Hi, CE/-Hi, MSB-LSB/-Lo  
Initialize Port C Outputs  
STAA PORTC  
*
* Call update subroutine  
*
BSR  
JMP  
UPDATE  
$E000  
Xfer 2 8-bit words to DAC8562  
Restart BUFFALO  
*
* Subroutine UPDATE  
*
UPDATE PSHX  
Save registers X, Y, and A  
PSHY  
PSHA  
*
* Enter contents of the Hi-byte input register  
*
LDAA #$0A  
STAA MSBS  
0,0,0,0;1,0,1,0  
MSBS are set to 0A (Hex)  
*
* Enter Contents of’ Lo-byte input register  
*
LDAA #$AA  
STAA LSBS  
1,0,1,0;1,0,1,0  
LSBS are set to AA (Hex)  
*
LDX  
LDY  
#MSBS  
#$1000  
Stack pointer at 1st byte to send via Port B  
Stack pointer at on-chip registers  
*
* Clear DAC output to zero  
*
BCLR PORTC,Y $04  
BSET PORTC,Y $04  
Assert CLR/  
De-assert CLR/  
*
* Loading input buffer latches  
*
BSET PORTC,Y $01  
LDAA 0,X  
STAA PORTB  
INX  
Set hi-byte register load  
TFRLP  
Get a byte to transfer via Port B  
Write data to input register  
Increment counter to next byte for transfer  
Are we done yet ?  
If yes, update DAC output  
Latch hi-byte register and set lo-byte register  
load  
CPX  
BEQ  
#LSBS+1  
DUMP  
BCLR PORTC,Y $01  
BRA TFRLP  
*
REV. A  
–15–  
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