DAC8562
Decoding Multiple DAC8562s
when PC1 is cleared. The DAC’s CLR input, controlled by the
M68HC11’s PC2 output line, provides an asynchronous clear
function that sets the DAC’s output to zero. Included in this sec-
tion is the source code for operating the DAC-8562–M68HC11
interface.
The CE function of the DAC8562 can be used in applications
to decode a number of DACs. In this application, all DACs re-
ceive the same input data; however, only one of the DACs’ CE
input is asserted to transfer its parallel input register contents
into the DAC. In this circuit, shown in Figure 40, the CE tim-
ing is generated by a 74HC139 decoder and should follow the
DAC8562’s standard timing requirements. To prevent timing
errors, the 74HC139 should not be activated by its ENABLE
input while the coded address inputs are changing. A simple
timing circuit, R1 and C1, connected to the DACs’ CLR pins
resets all DAC outputs to zero during power-up.
+5V
R1
C1
0.1µF
Ω
1k
V
OUT1
15
13
16
DAC-8562
#1
MICROPROCESSOR INTERFACING
DAC-8562–MC68HC11 INTERFACE
DATA
+5V
The circuit illustrated in Figure 41 shows a parallel interface be-
tween the DAC8562 and a popular 8-bit microcontroller, the
M68HC11, which is configured in a single-chip operating
mode. The interface circuit consists of a pair of 74ACT11373
transparent latches and an inverter. The data is loaded into the
latches in two 8-bit bytes; the first byte contains the four most
significant bits, and the lower 8 bits are in the second byte. Data
is taken from the microcontroller’s port B output lines, and
three interface control lines, CLR, CE, and MSB/LSB, are con-
trolled by the M68HC11's PC2, PC1, and PC0 output lines, re-
spectively. To transfer data into the DAC, PC0 is set, enabling
U1’s outputs. The first data byte is loaded into U1 where the
four least significant bits of the byte are connected to
V
OUT2
15
16
13
74HC139
16
4
5
6
0.1µF
DAC-8562
#2
1Y0
V
CC
ENABLE
1
1G
1A
1B
2G
1Y1
1Y2
2
3
V
CODED
ADDRESS
OUT3
15
16
7
1Y3
2Y0
2Y1
13
13
15
14
12
11
DAC-8562
#3
NC
NC
+5V
1k
Ω
2A
2B
13
8
10
9
NC
NC
2Y2
2Y3
V
OUT4
15
16
GND
DAC-8562
#4
MSB–DB8. PC0 is then cleared; this latches U1’s inputs and
enables U2’s outputs. U2s outputs now become DB7–DB0.
The DAC output is updated with the contents of U1 and U2
Figure 40. Decoding Multiple DAC8562s Using the CE Pin
74ACT11373
*M6BHC11
13
23
C
1
PC2
PC1
1D
1Q
CLR
CE
NC
NC
22
2
2D
2Q
3Q
21
20
3
4
74HC04
2
NC
NC
3D
4D
*DAC-8562
1
MSB/ LSB
PC0
4Q
5Q
15
16
1
U1
9
PC2
PC1
CLR
CE
5D
6D
10
16
15
14
24
6Q
7Q
9
11
12
MSB
7D
8D
8
7
DB10
8Q
DB9
U3
OC
6
5
DB8
74ACT11373
C
DB7
13
V
13
4
OUT
DB6
DB5
3
23
22
21
1
2
3
PB7
1D
2D
3D
1Q
2Q
3Q
4Q
2
PB6
PB5
DB4
DB3
1
19
18
17
20
1
4
PB4
PB3
PB2
PB1
PB0
DB2
DB1
4D
5D
6D
7D
U2
9
5Q
6Q
10
11
12
16
15
14
24
LSB
7Q
8Q
8D
OC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. DAC8562 to MC68HC11 Interface
–14–
REV. A
ADI [ ADI ]
