AT45DB081D
28. Revision History
Revision Level – Release Date History
A – November 2005
B – March 2006
Initial Release
Added Preliminary.
Added text, in “Programming the Configuration Register”, to indicate
that power cycling is required to switch to “power of 2” page size
after the opcode enable has been executed.
Added “Legacy Commands” table.
Corrected PA3 in opcode 50h for addressing sequence with
standard page size. Corrected Chip Erase opcode from 7CH to
C7H. Clarified the commands B and C usage for operation mode.
C – July 2006
Removed Preliminary.
D – November 2006
E – February 2007
Added errata regarding Chip Erase.
Changed various timing parameters under Table 18-4.
Removed RDY/BUSY pin references.
Removed SER/BYTE statement from SI and SO pin descriptions in
Table 2-1.
Added additional text to “power of 2” binary page size option.
F – August 2007
G – January 2008
Changed tVSCL from 50μs to 70μs.
Changed tRDPD from 30μs to 35μs.
Added additional text, in “power of 2” binary page size option, to
indicate that the address format is changed for devices with page
size set to 256-bytes.
Corrected typographical error to indicate that Figure 13-1 indicates
Program Configuration Register.
H – January 2008
I – April 2008
Removed DataFlash card pinout.
Added part number ordering code details for suffixes SL954/955
Added ordering code details.
J – February 2009
Changed tDIS (Typ and Max) to 27ns and 35ns, respectively.
Changed Deep Power-Down Current values
- Increased typical value from 5μA to 15μA.
- Increased maximum value from 15μA to25 μA.
K – March 2009
L – April 2009
Updated Absolute Maximum Ratings
Removed Chip Erase Errata
Changed tSE (Typ) 1.6 to 0.7 and (Max) 5 to 1.3
Changed tCE (Typ) TBD to 7 and (Max) TBD to 22
M – May 2010
Changed from 10,000 to 20,000 cumulative page erase/program
operations and added the contact statement in section 11.3.
N – November 2012
O - January 2013
Update to Adesto.
change to 2 buffers in diagram 22-1
51
3596O–DFLASH–1/2013
ADI [ ADI ]
