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AT45DB081D-SU 参数 Datasheet PDF下载

AT45DB081D-SU图片预览
型号: AT45DB081D-SU
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位2.5V或2.7V的DataFlash [8-megabit 2.5V or 2.7V DataFlash]
分类和应用: 内存集成电路光电二极管异步传输模式PCATM时钟
文件页数/大小: 53 页 / 1867 K
品牌: ADI [ ADI ]
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13.1 Programming the Configuration Register  
To program the Configuration Register for “power of 2” binary page size, the CS pin must first be  
asserted as it would be with any other command. Once the CS pin has been asserted, the  
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The  
4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the  
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate  
the internally self-timed program cycle. The programming of the Configuration Register should  
take place in a time of tP, during which time the Status Register will indicate that the device is  
busy. The device must be power-cycled after the completion of the program cycle to set the  
“power of 2” page size. If the device is powered-down before the completion of the program  
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should  
check bit zero of the status register to see whether the page size was configured for binary page  
size. If not, the command can be re-issued again.  
Table 13-1. Programming the Configuration Register  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Power of Two Page Size  
3DH  
2AH  
80H  
A6H  
Figure 13-1. Program Configuration Register  
CS  
Opcode  
Byte 1  
Opcode  
Byte 2  
Opcode  
Byte 3  
Opcode  
Byte 4  
SI  
Each transition  
represents 8 bits  
14. Manufacturer and Device ID Read  
Identification information can be read from the device to enable systems to electronically query  
and identify the device while it is in system. The identification method and the command opcode  
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI  
Compatible Serial Interface Memory Devices”. The type of information that can be read from the  
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-  
dor specific Extended Device Information.  
To read the identification information, the CS pin must first be asserted and the opcode of 9FH  
must be clocked into the device. After the opcode has been clocked in, the device will begin out-  
putting the identification data on the SO pin during the subsequent clock cycles. The first byte  
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.  
The fourth byte output will be the Extended Device Information String Length, which will be 00H  
indicating that no Extended Device Information follows. As indicated in the JEDEC standard,  
reading the Extended Device Information String Length and any subsequent data is optional.  
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put  
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not  
require that a full byte of data be read.  
24  
AT45DB081D  
3596O–DFLASH–1/2013  
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