ADV7390/ADV7391/ADV7392/ADV7393
CIRCUIT FREQUENCY RESPONSE
0
PRINTED CIRCUIT BOARD (PCB) LAYOUT
0
–10
–20
–30
–40
–50
–60
–70
–80
24n
21n
18n
15n
12n
9n
–30
The ADV739x is a highly integrated circuit containing both
precision analog and high speed digital circuitry. It has been
designed to minimize interference effects on the integrity of the
analog circuitry by the high speed digital circuitry. It is imperative
that these same design and layout techniques be applied to the
system-level design so that optimal performance is achieved.
MAGNITUDE (dB)
–60
–90
PHASE (Degrees)
–120
–150
–180
–210
–240
The layout should be optimized for lowest noise on the
ADV739x power and ground planes by shielding the digital
inputs and providing good power supply decoupling.
GROUP DELAY (Seconds)
6n
3n
0
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 89. Output Filter Plot for SD, 16× Oversampling
Component Placement
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry from analog circuitry.
CIRCUIT FREQUENCY RESPONSE
0
480
18n
16n
–10
400
320
240
160
80
MAGNITUDE (dB)
The external loop filter components and components connected
to the COMP and RSET pins should be placed as close as possible
to and on the same side of the PCB as the ADV739x. Adding
vias to the PCB to get the components closer to the ADV739x is
not recommended.
–20
–30
–40
–50
–60
–70
–80
–90
14n
PHASE
(Degrees)
12n
10n
8n
GROUP DELAY (Seconds)
It is recommended that the ADV739x be placed as close as
possible to the output connector, with the DAC output traces as
short as possible.
0
6n
–80
–160
–240
4n
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV739x. The termination resistors should overlay the
PCB ground plane.
2n
0
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 90. Output Filter Plot for ED, 8× Oversampling
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV739x to
minimize the possibility of noise pickup from neighboring
circuitry, and to minimize the effect of trace capacitance on
output bandwidth. This is particularly important when
operating in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
CIRCUIT FREQUENCY RESPONSE
0
200
120
40
PHASE
(Degrees)
MAGNITUDE (dB)
–10
–20
–30
–40
–50
GROUP DELAY (Seconds)
Power Supplies
It is recommended that a separate regulated supply be provided
for each power domain (VAA, VDD, VDD_IO, and PVDD). For
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the VAA and PVDD power domains. Each power supply should be
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
–40
–120
–200
1
10
100
FREQUENCY (MHz)
Figure 91. Output Filter Plot for HD, 4× Oversampling
Rev. 0 | Page 63 of 96
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