ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL APPLICATION CIRCUIT
FERRITE BEAD
NOTES
V
DD_IO
V
POWER
DD_IO
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED
TO THE COMP, R
CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS THE ADV739x.
33µF
10µF
0.1µF
0.01µF
SUPPLY
DECOUPLING
AND DAC OUTPUT PINS SHOULD BE LOCATED
SET
GND_IO
GND_IO
GND_IO GND_IO
FERRITE BEAD
PV
DD
2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS
CONFIGURABLE USING THE ALSB/SPI_SS PIN:
PV
SUPPLY
DECOUPLING
POWER
DD
33µF
10µF
0.1µF
0.01µF
PGND
PGND
FERRITE BEAD
PGND
PGND
2
ALSB/SPI_SS = 0, I C DEVICE ADDRESS = 0xD4 OR 0x54
2
ALSB/SPI_SS = 1, I C DEVICE ADDRESS = 0xD6 OR 0x56
V
V
AA
DD
V
POWER
AA
33µF
10µF
0.1µF
0.01µF
AGND
1µF
3. THE RESISTOR CONNECTED TO THE R
SET
TOLERANCE.
PIN SHOULD HAVE A 1%
SUPPLY
DECOUPLING
AGND
FERRITE BEAD
AGND
AGND
AGND
4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL-
DRIVE (R
= 510Ω, R = 37.5Ω).
L
SET
V
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DD
33µF
10µF
0.1µF
0.01µF
DGND
DGND
DGND
DGND
V
AA
2.2nF
P0
P1
P2
P3
P4
P5
P6
P7
COMP
R
SET
ADV739x
510Ω
AGND
PIXEL PORT INPUTS
DACs 1 TO 3 FULL DRIVE OPTION
(RECOMMENDED)
P8
P9
DACs 1 TO 3 LOW DRIVE OPTION
OPTIONAL LPF
OPTIONAL LPF
P10
P11
P12
P13
P14
P15
DAC 1
DAC 2
DAC 3
DAC 1
DAC 2
DAC 3
ADV7392/
ADV7393
ONLY
R
SET
4.12kΩ
OPTIONAL LPF
75Ω
75Ω
75Ω
AGND
ADA4411-3
AGND AGND AGND
75Ω
DAC 1
DAC 2
DAC 3
DAC 1
DAC 2
DAC 3
HSYNC
VSYNC
CONTROL
INPUTS/OUTPUTS
LPF
300Ω
CLKIN
CLOCK INPUT
AGND
ADA4411-3
SDA/SCLK
SCL/MOSI
SFL/MISO
MPU PORT
INPUTS/OUTPUTS
75Ω
ALSB/SPI_SS
LPF
300Ω
RESET
AGND
EXTERNAL LOOP FILTER
ADA4411-3
PV
DD
12nF
75Ω
EXT_LF
LPF
150nF
170Ω
300Ω
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV739x.
AGND
AGND PGND DGND DGND GND_IO
AGND PGND DGND DGND GND_IO
Figure 92. ADV739x Typical Application Circuit
Rev. 0 | Page 65 of 96
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