ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or
HSYNC
VSYNC
external synchronization signals provided on the
and
pins (see Table 49 to Table 51).
pins (see Table 48). It is also possible to output synchronization
HSYNC VSYNC
signals on the
and
Table 48. Timing Synchronization Signal Input Options
Signal
Pin
Condition
HSYNC
HSYNC
VSYNC
HSYNC
VSYNC
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
SD
SD
In
VSYNC
/FIELD In
HSYNC
ED/HD
ED/HD
In
VSYNC
/FIELD In
1 SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 49. Timing Synchronization Signal Output Options
Signal
Pin
Condition
HSYNC
HSYNC
VSYNC
HSYNC
VSYNC
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2
SD
SD
Out
VSYNC
/FIELD Out
HSYNC
ED/HD
ED/HD
Out
VSYNC
/FIELD Out
1 ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
2 ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
1
HSYNC
Table 50.
Output Control
ED/HD HSYNC
Control
Format (0x30, Bit 2) (0x34, Bit 1)
ED/HD Sync
Output Enable
(0x02, Bit 7)
SD Sync
Output Enable
(0x02, Bit 6)
ED/HD Input Sync
Signal on HSYNC Pin
Duration
x
x
x
x
0
0
0
1
Tristate.
–
HSYNC
See Error! Reference
source not found..
Pipelined SD
.
0
1
0
0
1
1
x
x
HSYNC
HSYNC
HSYNC
As per timing.
Pipelined ED/HD
.
Same as line blanking
interval.
Pipelined ED/HD
AV Code H bit.
based on
based on
x
1
1
x
HSYNC
Same as embedded
Pipelined ED/HD
HSYNC
.
horizontal counter.
1
HSYNC
HSYNC
HSYNC
pulse is aligned with the falling edge of the embedded in the output video.
In all ED/HD standards where there is a
output, the start of the
1
VSYNC
Table 51.
Output Control
ED/HD VSYNC
Control
(0x34, Bit 2)
ED/HD Input
Sync Format
(0x30, Bit 2)
ED/HD Sync
Output Enable Output Enable
(0x02, Bit 7)
SD Sync
Signal on VSYNC Pin
(0x02, Bit 6)
Video Standard
Duration
x
x
x
x
0
0
0
1
x
Tristate.
–
Interlaced
VSYNC
/Field. See Error!
Pipelined SD
Reference source
not found..
0
1
1
x
x
0
0
0
1
1
1
1
1
1
1
x
x
x
x
x
x
VSYNC
VSYNC
As per or
Field signal timing.
Field.
Pipelined ED/HD
or field signal.
All HD interlaced
standards
All ED/HD progressive
standards
Pipelined Field signal
based on AV Code F bit.
VSYNC
Vertical blanking
interval.
Pipelined
based on
AV Code V bit.
All ED/HD standards
except 525p
VSYNC
based on vertical counter.
VSYNC
Pipelined ED/HD
based on vertical counter.
Aligned with
serration lines.
Pipelined ED/HD
525p
Vertical blanking
interval.
1
VSYNC
VSYNC
VSYNC
pulse is aligned with the falling edge of the embedded in the output video.
In all ED/HD standards where there is a
output, the start of the
Rev. 0 | Page 61 of 96
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