ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0xF3
AFE Control 1
AA_FILT_EN[2:0].
Antialiasing filter enable.
0
Antialiasing Filter 1 disabled
AA_FILT_MAN_OVR must
be enabled to change
settings defined by
INSEL[3:0]
1
Antialiasing Filter 1 enabled
Antialiasing Filter 2 disabled
Antialiasing Filter 2 enabled
Antialiasing Filter 3 disabled
0
1
0
1
Antialiasing Filter 3
enabled
AA_FILT_MAN_OVR.
Antialiasing filter
override.
0
1
Override disabled
Override enabled
Reserved.
0
0
0
0
0xF4
Drive Strength
DR_STR_S[1:0]. Selects
the drive strength for
the sync output signals.
0
0
0
1
Low drive strength (1×)
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Low drive strength (1×)
DR_STR_C[1:0]. Selects
the drive strength for
the clock output signal.
0
0
0
1
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Low drive strength (1×)
DR_STR[1:0]. Selects the
drive strength for the
data output signals.
Can be increased or
decreased for EMC or
crosstalk reasons.
0
0
0
1
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Reserved.
x
x
0xF8
IF Comp Control
IFFILTSEL[2:0]. IF filter
selection for PAL and
NTSC.
0
0
0
Bypass mode
0 dB
2 MHz
−3 dB
5 MHz
−2 dB
NTSC filters
0
0
0
1
0
1
1
0
1
0
1
0
−6 dB
+3.5 dB
+5 dB
−10 dB
Reserved
3 MHz
−2 dB
6 MHz
+2 dB
+3 dB
+5 dB
PAL filters
1
1
1
0
1
1
1
0
1
−5 dB
−7 dB
Reserved.
0
0
0
0
0
Rev. A | Page 96 of 112
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