ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x4A
Interrupt Status 3
(Read Only)
SD_OP_CHNG_Q. SD 60 Hz/50 Hz
frame rate at output.
0
No change in SD signal standard
detected at the output
These bits can be cleared
and masked by Registers
0x4B and 0x4C,
1
A change in SD signal standard is
detected at the output
respectively
SD_V_LOCK_CHNG_Q.
SD_H_LOCK_CHNG_Q.
0
1
No change in SD vsync lock status
SD vsync lock status has changed
No change in SD hsync lock status
SD hsync lock status has changed
0
1
SD_AD_CHNG_Q. SD autodetect
changed.
0
1
No change in AD_RESULT[2:0] bits in
Status Register 1
AD_RESULT[2:0] bits in Status Register 1
have changed
SCM_LOCK_CHNG_Q. SECAM lock.
PAL_SW_LK_CHNG_Q.
0
1
No change in SECAM lock status
SECAM lock status has changed
0
1
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Reserved.
x
x
x
Not used
Reserved.
x
x
x
Not used
0x4B
Interrupt Clear 3
(Write only)
SD_OP_CHNG_CLR.
0
1
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
SD_V_LOCK_CHNG_CLR.
SD_H_LOCK_CHNG_CLR.
SD_AD_CHNG_CLR.
0
1
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_AD_CHNG_Q bit
Do not clear
SCM_LOCK_CHNG_CLR.
PAL_SW_LK_CHNG_CLR.
0
1
Clears SCM_LOCK_CHNG_Q bit
Do not clear
0
1
Clears PAL_SW_LK_CHNG_Q bit
Not used
Reserved.
Reserved.
Not used
0x4C
Interrupt Mask 3
(Read/Write)
SD_OP_CHNG_MSK
0
1
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
.
SD_V_LOCK_CHNG_ MSK
0
1
.
SD_H_LOCK_CHNG_ MSK
0
1
.
SD_AD_CHNG_ MSK
0
1
.
SCM_LOCK_CHNG_ MSK
0
1
.
PAL_SW_LK_CHNG_ MSK
0
1
.
Reserved.
Reserved.
Not used
Rev. A | Page 100 of 112
ADI [ ADI ]
