ADV7180
64-LEAD LQFP
RESET
SDATA
FIELD
DGND
DVDD
GPO2
GPO3
SCLK
ALSB
A
IN
6
48
A
IN
5
PIN 1
47
A
IN
4
46
A
IN
3
45
NC
44
NC
43
AGND
42
NC
41
NC
40
AVDD
39
VREFN
38
VREFP
37
AGND
36
A
IN
2
35
A
IN
1
34
TEST_0
33
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P12
P13
P14
P15
64 63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
INTRQ
HS
DGND
DVDDIO
P11
P10
P9
P8
SFL
1
2
3
4
5
6
7
8
9
ADV7180
LQFP
TOP VIEW
(Not to Scale)
DGND
10
DVDDIO
11
GPO1
12
GPO0
13
P7
14
P6
15
P5
16
LLC
XTAL
XTAL1
PWRDWN
ELPF
P4
P3
P2
P1
P0
DGND
PVDD
NC
NC
NC
VS
AGND
DVDD
NC = NO CONNECT
Figure 8. 64-Lead LQFP Pin Configuration
Table 9. Pin Function Description for the ADV7180 LQFP-64
Pin No.
3, 10, 24, 57
32, 37, 43
4, 11
23, 58
40
31
38
39
35, 36, 46 to 49
27, 28, 33, 41, 42,
44, 45, 50
5 to 8, 14 to 19,
25, 26, 59 to 62
2
64
63
1
53
54
52
29
30
51
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
VREFP
VREFN
A
IN
1 to A
IN
6
NC
P11 to P8,
P7 to P2, P1,
P0, P15 to P12
HS
VS
FIELD
INTRQ
SDATA
SCLK
ALSB
PWRDWN
ELPF
RESET
O
Type
G
G
P
P
P
P
O
O
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Analog Video Input Channels.
No Connect Pins. These pins are not connected internally.
Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.
O
O
O
O
I/O
I
I
I
I
I
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I
2
C address for the ADV7180. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Rev. A | Page 13 of 113
05700-008
AD [ ANALOG DEVICES ]
