ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
PIN 1
DVDDIO
SFL
DGND
DVDDIO
P7
1
2
3
4
5
6
7
8
9
30
29
A
A
3
2
IN
IN
INDICATOR
28 AGND
27 AVDD
26 VREFN
25 VREFP
24 AGND
23 A 1
22 TEST_0
21 AGND
ADV7180
LFCSP
P6
P5
P4
P3
TOP VIEW
(Not to Scale)
IN
P2 10
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No.
3, 15, 35, 40
21, 24, 28
1, 4
14, 36
27
Mnemonic
Type
Function
DGND
AGND
DVDDIO
DVDD
AVDD
G
G
P
P
P
P
I
O
O
O
Ground for Digital Supply.
Ground for Analog Supply.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
20
PVDD
23, 29, 30
5 to 10, 16, 17
39
AIN1 to AIN3
P7 to P2, P1, P0
HS
38
INTRQ
37
33
34
32
VS/FIELD
SDATA
SCLK
O
I/O
I
I
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
ALSB
Selects the I2C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a
write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.
31
11
RESET
LLC
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.
O
13
12
XTAL
I
Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal, or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
XTAL1
O
18
19
PWRDWN
ELPF
I
I
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.
2
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
26
25
22
VREFN
VREFP
TEST_0
O
O
I
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
This pin must be tied to DGND.
Rev. A | Page 12 of 112
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