ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
DGND
HS
INTRQ
VS/FIELD
DVDD
DGND
SCLK
SDATA
ALSB
RESET
DVDDIO
1
SFL
2
DGND
3
DVDDIO
4
P7
5
P6
6
P5
7
P4
8
P3
9
P2
10
40
39
38
37
36
35
34
33
32
31
PIN 1
INDICATOR
ADV7180
LFCSP
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
A
IN
3
A
IN
2
AGND
AVDD
VREFN
VREFP
AGND
A
IN
1
TEST_0
AGND
LLC
XTAL1
XTAL
DVDD
DGND
P1
P0
PWRDWN
ELPF
PVDD
11
12
13
14
15
16
17
18
19
20
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No.
3, 15, 35, 40
21, 24, 28
1, 4
14, 36
27
20
23, 29, 30
5 to 10, 16, 17
39
38
37
33
34
32
31
11
13
12
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
A
IN
1 to A
IN
3
P7 to P2, P1, P0
HS
INTRQ
VS/FIELD
SDATA
SCLK
ALSB
RESET
LLC
XTAL
XTAL1
Type
G
G
P
P
P
P
I
O
O
O
O
I/O
I
I
I
O
I
O
Function
Ground for Digital Supply.
Ground for Analog Supply.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
Selects the I
2
C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a
write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.
Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal, or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
This pin must be tied to DGND.
Rev. A | Page 12 of 112
18
19
2
PWRDWN
ELPF
SFL
I
I
O
26
25
22
VREFN
VREFP
TEST_0
O
O
I
05700-007
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