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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
 浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第89页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第90页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第91页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第92页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第94页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第95页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第96页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第97页  
Data Sheet  
ADV7180  
Bits  
(Shading Indicates Default State)  
Subaddress  
Register  
Bit Description  
7
6
5
4
3
2
1
0
Comments  
Notes  
GDECOL[15:8]; see the  
Comments column  
0
0
0
0
0
0
0
0
GDECOL[15:0]: 16 individual enable bits  
that select the lines of video (odd field  
Line 10 to Line 25) that the decoder  
checks for Gemstar-compatible data  
LSB = Line 10,  
MSB = Line 25,  
0x4A  
Gemstar  
Control 3  
Default = do not  
check for Gemstar-  
compatible data on  
any lines [10 to 25]  
in odd fields  
GDECOL[7:0]  
0
0
0
0
0
0
0
0
0x4B  
Gemstar  
Control 4  
GDECAD; controls the  
0
1
Split data into half-byte  
To avoid 00/FF code  
0x4C  
Gemstar  
Control 5  
manner decoded Gemstar  
data is inserted into the  
horizontal blanking period  
Output in straight 8-bit format  
GDE_SEL_OLD_ADF  
Reserved  
0
Enables a new ancillary data system  
Undefined  
x
x
x
x
x
x
0x4D  
CTI DNR  
Control 1  
CTI_EN; CTI enable  
0
1
Disable CTI  
Enable CTI  
CTI_AB_EN; enables the  
mixing of the transient  
improved chroma with  
the original signal  
0
1
Disable CTI alpha blender  
Enable CTI alpha blender  
CTI_AB[1:0]; controls the  
behavior of the alpha-  
blend circuitry  
0
0
1
1
0
1
0
1
Sharpest mixing  
Sharp mixing  
Smooth mixing  
Smoothest mixing  
Set to default  
Reserved  
0
DNR_EN; enable or bypass  
the DNR block  
0
1
Bypass the DNR block  
Enable the DNR block  
Set to default  
Reserved  
1
0
1
0
0x4E  
0x50  
0x51  
CTI DNR  
Control 2  
CTI_C_TH[7:0]; specifies  
how big the amplitude  
step must be to be steep-  
ened by the CTI block  
0
0
0
1
1
0
0
0
0
0
0
Set to 0x04 for AV input;  
set to 0x0A for tuner input  
CTI DNR  
Control 4  
DNR_TH[7:0]; specifies  
the maximum edge that is  
interpreted as noise and is  
therefore blanked  
0
0
0
Lock count  
CIL[2:0]; count into lock  
determines the number of  
lines the system must  
remain in lock before  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
One line of video  
Two lines of video  
Five lines of video  
10 lines of video  
100 lines of video  
500 lines of video  
1000 lines of video  
100,000 lines of video  
1 line of video  
2 lines of video  
5 lines of video  
10 lines of video  
100 lines of video  
500 lines of video  
1000 lines of video  
100,000 lines of video  
Over field with vertical info  
Line-to-line evaluation  
showing a locked status  
COL[2:0]; count out of  
lock determines the  
number of lines the  
system must remain out-  
of-lock before showing a  
lost-locked status  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SRLS; select raw lock signal;  
selects the determination  
of the lock status  
0
1
FSCLE; fSC lock enable  
0
1
Lock status set only by horizontal lock  
Lock status set by horizontal lock and  
subcarrier lock  
0x58  
VS/FIELD  
pin control  
VS/FIELD; VSYNC or FIELD  
output; 40-lead and  
32-lead LFCSP only  
0
1
FIELD  
VSYNC  
Pin 37 on 40-lead  
LFCSP, Pin 31 on  
32-lead LFCSP  
Reserved  
0
Set to default  
ADC sampling control  
0
1
ADC sampling control  
Y/C mode only  
Set to default  
Mandatory write  
Reserved  
0
0
0
0
0
Rev. G | Page 93 of 120  
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