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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
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Data Sheet  
ADV7180  
AD_SECAM_EN, Enable Autodetection of SECAM,  
Address 0x07[6]  
AD_PAL_EN, Enable Autodetection of PAL B/D/I/G/H,  
Address 0x07[0]  
Setting AD_SECAM_EN to 0 (default) disables the autodetection  
of SECAM.  
Setting AD_PAL_EN to 0 (default) disables the detection of  
standard PAL.  
Setting AD_SECAM_EN to 1 enables the detection of SECAM.  
Setting AD_PAL_EN to 1 enables the detection of standard PAL.  
SFL_INV, Subcarrier Frequency Lock Inversion  
AD_N443_EN, Enable Autodetection of NTSC 4.43,  
Address 0x07[5]  
This bit controls the behavior of the PAL switch bit in the SFL  
(genlock telegram) data stream. It was implemented to solve  
some compatibility issues with video encoders. It solves two  
problems.  
Setting AD_N443_EN to 0 disables the autodetection of NTSC  
style systems with a 4.43 MHz color subcarrier.  
Setting AD_N443_EN to 1 (default) enables the detection of  
NTSC style systems with a 4.43 MHz color subcarrier.  
First, the PAL switch bit is only meaningful in PAL. Some  
encoders (including Analog Devices encoders) also look at the  
state of this bit in NTSC.  
AD_P60_EN, Enable Autodetection of PAL 60,  
Address 0x07[4]  
Second, there was a design change in Analog Devices encoders  
from ADV717x to ADV719x. The older versions used the SFL  
(genlock telegram) bit directly, whereas the newer ones invert  
the bit prior to using it. The reason for this is that the inversion  
compensated for the one line delay of an SFL (genlock telegram)  
transmission.  
Setting AD_P60_EN to 0 disables the autodetection of PAL  
systems with a 60 Hz field rate.  
Setting AD_P60_EN to 1 (default) enables the detection of PAL  
systems with a 60 Hz field rate.  
AD_PALN_EN, Enable Autodetection of PAL N,  
Address 0x07[3]  
As a result, for the ADV717x and ADV73xx encoders, the PAL  
switch bit in the SFL (genlock telegram) must be 0 for NTSC to  
work. For the ADV7194 video encoder, the PAL switch bit in the  
SFL must be 1 to work in NTSC. If the state of the PAL switch bit  
is wrong, a 180° phase shift occurs.  
Setting AD_PALN_EN to 0 (default) disables the detection of  
the PAL N standard.  
Setting AD_PALN_EN to 1 enables the detection of the PAL N  
standard.  
In a decoder/encoder back-to-back system in which SFL is used,  
this bit must be set up properly for the specific encoder used.  
AD_PALM_EN, Enable Autodetection of PAL M,  
Address 0x07[2]  
SFL_INV, Subcarrier Frequency Lock Inversion,  
Address 0x41[6]  
Setting AD_PALM_EN to 0 (default) disables the autodetection  
of PAL M.  
Setting SFL_INV to 0 (default) makes the part SFL compatible  
with the ADV717x and ADV73xx video encoders.  
Setting AD_PALM_EN to 1 enables the detection of PAL M.  
AD_NTSC_EN, Enable Autodetection of NTSC,  
Address 0x07[1]  
Setting SFL_INV to 1 makes the part SFL compatible with the  
ADV7194 video encoder.  
Setting AD_NTSC_EN to 0 (default) disables the detection of  
standard NTSC.  
Lock Related Controls  
Lock information is presented to the user through Bits[1:0] of  
the Status 1 register (see the Status 1[7:0], Address 0x10[7:0]  
section). Figure 19 outlines the signal flow and the controls  
available to influence the way the lock status information is  
generated.  
Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.  
SELECT THE RAW LOCK SIGNAL  
SRLS  
FILTER THE RAW LOCK SIGNAL  
CIL[2:0], COL[2:0]  
TIME_WIN  
FREE_RUN  
1
0
0
1
COUNTER INTO LOCK  
COUNTER OUT OF LOCK  
STATUS 1[0]  
STATUS 1[1]  
f
LOCK  
SC  
MEMORY  
TAKE f LOCK INTO ACCOUNT  
SC  
FSCLE  
Figure 19. Lock Related Signal Path  
Rev. G | Page 27 of 120  
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