Data Sheet
ADV7180
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1[7:0]
DEF_Y[5:0], Default Value Y, Address 0x0C[7:2]
This register allows the user to select an offset for the Cb channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
When the ADV7180 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
Table 30. SD_OFF_Cb Function
SD_OFF_Cb[7:0] Description
•
If the DEF_VAL_AUTO_EN bit is set to high and the
ADV7180 has lost lock to the input video signal. This is
the intended mode of operation (automatic mode).
The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that may be useful
during configuration.
0x80 (default)
0x00
0xFF
0 mV offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
•
SD_OFF_Cr[7:0], SD Offset Cr Channel, Address 0xE2[7:0]
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
Register 0x0C has a default value of 0x36.
Table 31. SD_OFF_Cr Function
SD_OFF_Cr[7:0]
0x80 (default)
0x00
Description
0 mV offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
DEF_C[7:0], Default Value C, Address 0x0D[7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if
0xFF
BRI[7:0], Brightness Adjust, Address 0x0A[7:0]
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7180 cannot lock to the input video (automatic mode).
DEF_VAL_EN bit is set to high (forced output).
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
•
Table 32. BRI Function
The data that is finally output from the ADV7180 for the
chroma side is Cr[3:0] = {DEF_C[7:4], 0, 0, 0, 0}, and
Cb[3:0] = {DEF_C[3:0], 0, 0, 0, 0}.
BRI[7:0]
0x00 (default)
0x7F
Description
Offset of the luma channel = 0 IRE
Offset of the luma channel = +30 IRE
Offset of the luma channel = −30 IRE
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
0x80
DEF_VAL_EN, Default Value Enable, Address 0x0C[0]
HUE[7:0], Hue Adjust, Address 0x0B[7:0]
This bit forces the use of the default values for Y, Cr, and Cb. See
the descriptions in the DEF_Y[5:0], Default Value Y, Address
0x0C[7:2] and DEF_C[7:0], Default Value C, Address 0x0D[7:0]
sections for additional information. In this mode, the decoder
also outputs a stable 27 MHz clock, HS, and VS.
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
HUE[7:0] has a range of 90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it applies only to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values.
This overrides picture data even if the decoder is locked.
Table 33. HUE Function
HUE[7:0]
0x00 (default)
0x7F
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
0x80
Rev. G | Page 29 of 120
ADI [ ADI ]
