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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
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ADV7180  
Data Sheet  
GLOBAL STATUS REGISTER  
Four registers provide summary information about the video  
decoder. The IDENT register allows the user to identify the  
revision code of the ADV7180. The other three registers (0x10,  
0x12, and 0x13) contain status bits from the ADV7180.  
Table 21. Status 1 Function  
Status 1[7:0]  
Bit Name  
Description  
0
1
IN_LOCK  
LOST_LOCK  
In lock (now)  
Lost lock (since last read of  
this register)  
fSC locked (now)  
AGC follows peak white  
algorithm  
Result of autodetection  
Result of autodetection  
Result of autodetection  
Color kill active  
IDENTIFICATION  
IDENT[7:0], Address 0x11[7:0]  
2
3
FSC_LOCK  
FOLLOW_PW  
This is the register identification of the ADV7180s revision.  
Table 19 describes the various versions of the ADV7180.  
4
5
6
7
AD_RESULT[0]  
AD_RESULT[1]  
AD_RESULT[2]  
COL_KILL  
Table 19. IDENT CODE  
IDENT[7:0]  
0x1B1  
0x1C1  
Description  
Initial release silicon  
Improved ESD and PDC fix  
STATUS 2  
Status 2[7:0], Address 0x12[7:0]  
0x1E  
48-lead and 32-lead devices only  
1 64-lead and 40-lead models only.  
Table 22. Status 2 Function  
STATUS 1  
Status 1[7:0], Address 0x10[7:0]  
Status 2[7:0]  
Bit Name  
Description  
0
MVCS DET  
Detected Macrovision color  
striping  
Macrovision color striping  
protection; conforms to Type 3  
if high, Type 2 if low  
Detected Macrovision pseudo-  
sync pulses  
Detected Macrovision AGC  
pulses  
This read-only register provides information about the internal  
status of the ADV7180.  
1
MVCS T3  
See the CIL[2:0], Count Into Lock, Address 0x51[2:0] section  
and the COL[2:0], Count Out of Lock, Address 0x51[5:3]  
section for details on timing.  
2
3
MV PS DET  
MV AGC DET  
Depending on the setting of the FSCLE bit, the Status Register 0  
and Status Register 1 are based solely on horizontal timing  
information or on the horizontal timing and lock status of  
the color subcarrier. See the FSCLE, fSC Lock Enable, Address  
0x51[7] section.  
4
5
6
7
LL NSTD  
Line length is nonstandard  
fSC frequency is nonstandard  
FSC NSTD  
Reserved  
Reserved  
AUTODETECTION RESULT  
AD_RESULT[2:0], Address 0x10[6:4]  
STATUS 3  
Status 3[7:0], Address 0x13[7:0]  
The AD_RESULT[2:0] bits report back on the findings from the  
ADV7180 autodetection block. See the General Setup section for  
more information on enabling the autodetection block and the  
Autodetection of SD Modes section for more information on  
how to configure it.  
Table 23. Status 3 Function  
Status 3[7:0]  
Bit Name  
Description  
0
INST_HLOCK  
Horizontal lock indicator  
(instantaneous)  
1
2
GEMD  
SD_OP_50Hz  
Gemstar detect  
Flags whether 50 Hz or 60 Hz is  
present at output  
Table 20. AD_RESULT Function  
AD_RESULT[2:0]  
Description  
000  
001  
010  
011  
100  
101  
110  
111  
NTSC M/J  
NTSC 4.43  
PAL M  
PAL 60  
PAL B/G/H/I/D  
SECAM  
3
4
Reserved  
Reserved for future use  
FREE_RUN_ACT ADV7180 outputs a blue  
screen (see the DEF_VAL_EN,  
Default Value Enable,  
Address 0x0C[0] section)  
5
STD FLD LEN  
Field length is correct for  
currently selected video  
standard  
Interlaced video detected  
(field sequence found)  
PAL Combination N  
SECAM 525  
6
7
Interlaced  
PAL_SW_LOCK  
Reliable sequence of  
swinging bursts detected  
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